On 11 October 2016 at 02:24, David Gibson <da...@gibson.dropbear.id.au> wrote: > On Mon, Oct 10, 2016 at 03:10:33PM +0100, Peter Maydell wrote: >> On 10 October 2016 at 14:39, David Gibson <da...@gibson.dropbear.id.au> >> wrote: >> > In the overwhelming majority of cases the endianness of the device is >> > known independent of the guest CPU and board. >> >> We don't seem to model things that way: >> >> $ git grep '.endianness = DEVICE_NATIVE' |wc -l >> 341 >> $ git grep '.endianness = DEVICE_BIG' |wc -l >> 18 >> $ git grep '.endianness = DEVICE_LITTLE' |wc -l >> 172 > > Sigh. So, most of these are themselves mistakes. > > A lot of these are target specific devices that should be tagged with > their target's (notional) endianness, rather than NATIVE. That > covers:
> MICROBLAZE > hw/dma/xilinx_axidma.c 1 > hw/char/xilinx_uartlite.c 1 > hw/intc/xilinx_intc.c 1 > hw/net/xilinx_ethlite.c 1 > hw/timer/xilinx_timer.c 1 > hw/ssi/xilinx_spi.c 1 > --- > TOTAL 6 We build microblaze in both big and little endian configs... > MIPS > hw/mips 8 > hw/*/mips* 5 > hw/display/jazz_led.c 1 > hw/dma/rc4030.c 2 > hw/net/dp8393x.c 1 > hw/pci-host/bonito.c 5 > --- > TOTAL 22 Ditto MIPS. > SH > hw/sh4 4 > hw/*/sh_* 3 > hw/display/sm501.c 4 > --- > TOTAL 11 And SH. > XTENSA > hw/xtensa 3 And Xtensa. thanks -- PMM
