The current way we organize the IO windows into PCI space for the
pseries machine type has several problems.
- It makes it difficult to create very large MMIO spaces which is
necessary for certain PCI devices with very large BARs. This
problem has been known for a while.
- More recently we discovered a more serious problem: it prevents
more than 1TiB of RAM being added to a pseries guest.
- It doesn't make very efficient use of address space.
Fixing this is complicated by keeping migration from old versionss
working and working out what things belong on which side of the
abstraction barrier between the machine type and the host bridge
device.
This patch addresses all these problems. Patches 1-2/4 represent a
minimal fix for the most serious problem (the 1 TiB limit) - once
polished, I'll consider submiting these for the stable branch. 3-4/4
complete a more comprehensive fix.
David Gibson (4):
spapr_pci: Delegate placement of PCI host bridges to machine type
spapr: Adjust placement of PCI host bridge to allow > 1TiB RAM
spapr_pci: Add a 64-bit MMIO window
spapr: Improved placement of PCI host bridges in guest memory map
hw/ppc/spapr.c | 121 +++++++++++++++++++++++++++++++++++++++++++-
hw/ppc/spapr_pci.c | 90 ++++++++++++++++++++++----------
include/hw/pci-host/spapr.h | 24 ++++-----
include/hw/ppc/spapr.h | 5 ++
4 files changed, 199 insertions(+), 41 deletions(-)
--
2.7.4
