and also link the XICS object to each core as it is needed to do the
CPU setup.
Signed-off-by: Cédric Le Goater <c...@kaod.org>
---
hw/ppc/pnv.c | 18 ++++++++++++++++++
hw/ppc/pnv_core.c | 25 +++++++++++++++++++++----
include/hw/ppc/pnv.h | 2 ++
3 files changed, 41 insertions(+), 4 deletions(-)
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c
index 4a71b18bf38b..6335ca11efe7 100644
--- a/hw/ppc/pnv.c
+++ b/hw/ppc/pnv.c
@@ -32,6 +32,7 @@
#include "exec/address-spaces.h"
#include "qemu/cutils.h"
+#include "hw/ppc/xics.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/isa/isa.h"
@@ -223,6 +224,7 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
char *typename = pnv_core_typename(pcc->cpu_model);
size_t typesize = object_type_get_instance_size(typename);
int i;
+ int smt = 1; /* TCG does not support more for the moment */
pnv_xscom_populate(chip, fdt, 0);
@@ -230,6 +232,9 @@ static void powernv_populate_chip(PnvChip *chip, void *fdt)
PnvCore *pnv_core = PNV_CORE(chip->cores + i * typesize);
powernv_create_core_node(chip, pnv_core, fdt);
+
+ /* Interrupt presentation controllers (ICP). One per core. */
+ xics_native_populate_icp(chip, fdt, 0, pnv_core->pir, smt);
}
/* Put all the memory in one node on chip 0 until we find a way to
@@ -631,6 +636,9 @@ static void pnv_chip_init(Object *obj)
object_initialize(&chip->lpc, sizeof(chip->lpc), TYPE_PNV_LPC);
object_property_add_child(obj, "lpc", OBJECT(&chip->lpc), NULL);
+
+ object_initialize(&chip->xics, sizeof(chip->xics), TYPE_XICS_NATIVE);
+ object_property_add_child(obj, "xics", OBJECT(&chip->xics), NULL);
}
static void pnv_chip_realize(DeviceState *dev, Error **errp)
@@ -641,6 +649,7 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
char *typename = pnv_core_typename(pcc->cpu_model);
size_t typesize = object_type_get_instance_size(typename);
int i, core_hwid;
+ int smt = 1; /* TCG does not support more for the moment */
if (!object_class_by_name(typename)) {
error_setg(errp, "Unable to find PowerNV CPU Core '%s'", typename);
@@ -662,6 +671,13 @@ static void pnv_chip_realize(DeviceState *dev, Error
**errp)
return;
}
+ /* Set up Interrupt Controller before we create the VCPUs */
+ object_property_set_int(OBJECT(&chip->xics), smp_cpus * smt / smp_threads,
+ "nr_servers", &error_fatal);
+ object_property_set_bool(OBJECT(&chip->xics), true, "realized",
+ &error_fatal);
+ sysbus_mmio_map(SYS_BUS_DEVICE(&chip->xics), 0, PNV_XICS_BASE);
+
chip->cores = g_malloc0(typesize * chip->nr_cores);
for (i = 0, core_hwid = 0; (core_hwid < sizeof(chip->cores_mask) * 8)
@@ -684,6 +700,8 @@ static void pnv_chip_realize(DeviceState *dev, Error **errp)
object_property_set_int(OBJECT(pnv_core),
pcc->core_pir(chip, core_hwid),
"pir", &error_fatal);
+ object_property_add_const_link(OBJECT(pnv_core), "xics",
+ OBJECT(&chip->xics), &error_fatal);
object_property_set_bool(OBJECT(pnv_core), true, "realized",
&error_fatal);
object_unref(OBJECT(pnv_core));
diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c
index a1c8a14f06b6..fe18e3150f78 100644
--- a/hw/ppc/pnv_core.c
+++ b/hw/ppc/pnv_core.c
@@ -24,6 +24,7 @@
#include "hw/ppc/ppc.h"
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_core.h"
+#include "hw/ppc/xics.h"
static void powernv_cpu_reset(void *opaque)
{
@@ -54,7 +55,7 @@ static void powernv_cpu_reset(void *opaque)
env->msr |= MSR_HVB; /* Hypervisor mode */
}
-static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
+static void powernv_cpu_init(PowerPCCPU *cpu, XICSState *xics, Error **errp)
{
CPUPPCState *env = &cpu->env;
@@ -63,6 +64,12 @@ static void powernv_cpu_init(PowerPCCPU *cpu, Error **errp)
qemu_register_reset(powernv_cpu_reset, cpu);
powernv_cpu_reset(cpu);
+
+ /*
+ * XICS native cpu_setup() expects SPR_PIR to be set. So it needs
+ * to run after powernv_cpu_reset()
+ */
+ xics_cpu_setup(xics, cpu);
}
/*
@@ -110,7 +117,7 @@ static const MemoryRegionOps pnv_core_xscom_ops = {
.endianness = DEVICE_BIG_ENDIAN,
};
-static void pnv_core_realize_child(Object *child, Error **errp)
+static void pnv_core_realize_child(Object *child, XICSState *xics, Error
**errp)
{
Error *local_err = NULL;
CPUState *cs = CPU(child);
@@ -122,7 +129,7 @@ static void pnv_core_realize_child(Object *child, Error
**errp)
return;
}
- powernv_cpu_init(cpu, &local_err);
+ powernv_cpu_init(cpu, xics, &local_err);
if (local_err) {
error_propagate(errp, local_err);
return;
@@ -140,6 +147,7 @@ static void pnv_core_realize(DeviceState *dev, Error **errp)
void *obj;
int i, j;
char name[32];
+ XICSState *xics;
pc->threads = g_malloc0(size * cc->nr_threads);
for (i = 0; i < cc->nr_threads; i++) {
@@ -157,10 +165,19 @@ static void pnv_core_realize(DeviceState *dev, Error
**errp)
object_unref(obj);
}
+ /* get XICS object from chip */
+ obj = object_property_get_link(OBJECT(dev), "xics", &local_err);
+ if (!obj) {
+ error_setg(errp, "%s: required link 'xics' not found: %s",
+ __func__, error_get_pretty(local_err));
+ return;
+ }
+ xics = XICS_COMMON(obj);
+
for (j = 0; j < cc->nr_threads; j++) {
obj = pc->threads + j * size;
- pnv_core_realize_child(obj, &local_err);
+ pnv_core_realize_child(obj, xics, &local_err);
if (local_err) {
goto err;
}
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 3f24b87d199b..73d26c55d993 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -23,6 +23,7 @@
#include "hw/sysbus.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/ppc/pnv_lpc.h"
+#include "hw/ppc/xics.h"
#define TYPE_PNV_CHIP "powernv-chip"
#define PNV_CHIP(obj) OBJECT_CHECK(PnvChip, (obj), TYPE_PNV_CHIP)
@@ -55,6 +56,7 @@ typedef struct PnvChip {
void *cores;
PnvLpcController lpc;
+ XICSNative xics;
} PnvChip;
typedef struct PnvChipClass {
--
2.7.4
