On 09/27/2016 08:10 AM, Benjamin Herrenschmidt wrote: > On Tue, 2016-09-27 at 07:54 +0200, Cédric Le Goater wrote: >> >>> but I guess if you have the decoding of those "core" registers >>> here as well, then that doesn't make so much sense. > > Those core registers may well change with P9, we havne't looked closely > yet...
Neither have I ... qemu/pnv reaches the kernel but this is really a "Frankenstein P9". The interrupt controller is missing. C. >> yes and there is also the handling of the XSCOM failures. >> >> I can add some prologue handler to cover those "core" registers >> but adding a MemoryRegion, ops, init and mapping would be a lot >> of churn just to return 0. >> >> Thanks,
