>> +static ISABus *pnv_isa_create(PnvChip *chip)
>> +{
>> + PnvLpcController *lpc = &chip->lpc;
>> + ISABus *isa_bus;
>> + qemu_irq *irqs;
>> + PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip);
>> +
>> + /* Instanciate ISA bus. let isa_bus_new() create its own bridge on
>
> Instantiate has 3 't's and no 'c's; English orthography strikes again.
he :) thanks.
>> + * sysbus otherwise devices speficied on the command line will
>> + * fail to create.
>> + */
>> + isa_bus = isa_bus_new(NULL, &lpc->isa_mem, &lpc->isa_io,
>> + &error_fatal);
>
> It's not clear to me if this belongs in the chip code or on the lpc
> code - the lpc does create a device node as 'isa@', although it also
> does some other stuff.
In fact, the isabus in the qemu model is at the machine level, see below,
next to the 'Instanc^Htiate'.
each chip has a lpc controller but skiboot use a default one to route
the traffic. So we choose the chip[0] one for that.
Looking closer, I should make sure the "primary" cell is not added in the
device tree for chip_id != 0.
Thanks,
C.
>> +
>> + /* Not all variants have a working serial irq decoder. If not,
>> + * handling of LPC interrupts becomes a platform issue (some
>> + * platforms have a CPLD to do it).
>> + */
>> + if (pcc->chip_type == PNV_CHIP_POWER8NVL) {
>> + irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler, lpc, 16);
>> + } else {
>> + irqs = qemu_allocate_irqs(pnv_lpc_isa_irq_handler_cpld, NULL, 16);
>> + }
>> +
>> + isa_bus_irqs(isa_bus, irqs);
>> + return isa_bus;
>> +}
>> +
>> static void ppc_powernv_init(MachineState *machine)
>> {
>> PnvMachineState *pnv = POWERNV_MACHINE(machine);
>> @@ -389,6 +444,15 @@ static void ppc_powernv_init(MachineState *machine)
>> object_property_set_bool(chip, true, "realized", &error_fatal);
>> }
>> g_free(chip_typename);
>> +
>> + /* Instanciate ISA bus on chip 0 */
>> + pnv->isa_bus = pnv_isa_create(pnv->chips[0]);
>> +
>> + /* Create serial port */
>> + serial_hds_isa_init(pnv->isa_bus, MAX_SERIAL_PORTS);
>> +
>> + /* Create an RTC ISA device too */
>> + rtc_init(pnv->isa_bus, 2000, NULL);
>> }
>>
>> static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id)
>> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
>> index a30579a5817f..e75f937d40dd 100644
>> --- a/include/hw/ppc/pnv.h
>> +++ b/include/hw/ppc/pnv.h
>> @@ -123,6 +123,8 @@ typedef struct PnvMachineState {
>>
>> uint32_t num_chips;
>> PnvChip **chips;
>> +
>> + ISABus *isa_bus;
>> } PnvMachineState;
>>
>> #define POWERNV_FDT_ADDR 0x01000000
>
