On 2 August 2016 at 18:15, Cédric Le Goater <c...@kaod.org> wrote:
> This gives some explanation behind the magic number 0x120CE416.
>
> Signed-off-by: Cédric Le Goater <c...@kaod.org>
> ---
>
> Changes since v2:
>
> - more precise definitions of the hw-strap1 register
> - moved hw-strap1 to the board level.
>
> hw/arm/aspeed.c | 15 +++++-
> include/hw/misc/aspeed_scu.h | 118
> +++++++++++++++++++++++++++++++++++++++++++
> 2 files changed, 132 insertions(+), 1 deletion(-)
>
> diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c
> index 4226b8dcd95c..80907b4244ea 100644
> --- a/hw/arm/aspeed.c
> +++ b/hw/arm/aspeed.c
> @@ -39,8 +39,21 @@ enum {
> PALMETTO_BMC
> };
>
> +#define PALMETTO_BMC_HW_STRAP1 ( \
> + SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \
> + SCU_AST2400_HW_STRAP_DRAM_CONFIG(2 /* DDR3 with CL=6, CWL=5 */) | \
> + SCU_AST2400_HW_STRAP_ACPI_DIS | \
> + SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_48M_IN) | \
> + SCU_HW_STRAP_VGA_CLASS_CODE | \
> + SCU_HW_STRAP_LPC_RESET_PIN | \
> + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_M_S_EN) | \
> + SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \
> + SCU_HW_STRAP_SPI_WIDTH | \
> + SCU_HW_STRAP_VGA_SIZE_SET(VGA_16M_DRAM) | \
> + SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT))
> +
> static const AspeedBoardConfig aspeed_boards[] = {
> - [PALMETTO_BMC] = { "ast2400-a0", 0x120CE416 },
> + [PALMETTO_BMC] = { "ast2400-a0", PALMETTO_BMC_HW_STRAP1 },
> };
>
> static void aspeed_board_init_flashes(AspeedSMCState *s, const char
> *flashtype,
> diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h
> index fdfd982288f2..0761f0880c69 100644
> --- a/include/hw/misc/aspeed_scu.h
> +++ b/include/hw/misc/aspeed_scu.h
> @@ -36,4 +36,122 @@ typedef struct AspeedSCUState {
>
> extern bool is_supported_silicon_rev(uint32_t silicon_rev);
>
> +/*
> + * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions
> + * were added.
> + *
> + * Original header file :
> + * arch/arm/mach-aspeed/include/mach/regs-scu.h
> + *
> + * Copyright (C) 2012-2020 ASPEED Technology Inc.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License version 2 as
> + * published by the Free Software Foundation.
> + *
> + * History :
> + * 1. 2012/12/29 Ryan Chen Create
> + */
> +
> +/* Hardware Strapping Register definition (for Aspeed AST2400 SOC)
> + *
> + * 31:29 Software defined strapping registers
> + * 28:27 DRAM size setting (for VGA driver use)
> + * 26:24 DRAM configuration setting
> + * 23 Enable 25 MHz reference clock input
> + * 22 Enable GPIOE pass-through mode
> + * 21 Enable GPIOD pass-through mode
> + * 20 Disable LPC to decode SuperIO 0x2E/0x4E address
> + * 19 Disable ACPI function
> + * 23,18 Clock source selection
> + * 17 Enable BMC 2nd boot watchdog timer
> + * 16 SuperIO configuration address selection
> + * 15 VGA Class Code selection
> + * 14 Enable LPC dedicated reset pin function
> + * 13:12 SPI mode selection
> + * 11:10 CPU/AHB clock frequency ratio selection
> + * 9:8 H-PLL default clock frequency selection
> + * 7 Define MAC#2 interface
> + * 6 Define MAC#1 interface
> + * 5 Enable VGA BIOS ROM
> + * 4 Boot flash memory extended option
> + * 3:2 VGA memory size selection
> + * 1:0 BMC CPU boot code selection
> + */
> +#define SCU_AST2400_HW_STRAP_SW_DEFINE(x) (x << 29)
Brackets around macro parameters on the RHS, please (both
here and below).
Otherwise
Reviewed-by: Peter Maydell <peter.mayd...@linaro.org>
thanks
-- PMM
