On 2016-08-02 14:17, David Kiarie wrote: > > > On Tue, Aug 2, 2016 at 3:12 PM, Peter Xu <pet...@redhat.com > <mailto:pet...@redhat.com>> wrote: > > On Tue, Aug 02, 2016 at 02:58:55PM +0300, David Kiarie wrote: > > > Sure. David, so do you like to do it or I cook this patch? :) > > > > If there are no objections I will look at this employing Jan's approach: > > associating a write with an address space. > > Do you mean to translate current stl_le_phys() into something like > address_space_stl_le(), with MemTxAttrs? (in ioapic_service()) > > > I tried doing something like that but the write gets discarded > somewhere. I don't see the write from IOMMU side. > > > Also, IIUC we also need to tweak a little bit more for split irqchip > case in kvm_arch_fixup_msi_route(). Actually for this one, I think > maybe we can assume the requester ID be IOAPIC's when dev == NULL, > since HPET should not be using kernel irqchip, right? > > > I meant do have something like what is here > http://git.kiszka.org/?p=qemu.git;a=commitdiff;h=4f27331e7769a571c7d7fb61cf75e1b2fe908f85 > >
This didn't take irq routes into account that start with in-kernel devices. Peter is right, there is more than just patching the MSI write handlers in the IOMMUs. Jan -- Siemens AG, Corporate Technology, CT RDA ITP SES-DE Corporate Competence Center Embedded Linux
