This series contains 11 new instructions for POWER9 described in ISA3.0.
Patches:
01-02: Changes following instructions:
divd[u][o][.]: Divide Doubleword Signed/Unsigned
divw[u][o][.]: Divide Word Signed/Unsigned
03: dtstsfi[q] : DFP Test Significance Immediate [Quad]
04: vabsdub : Vector Absolute Difference Unsigned Byte
vabsduh : Vector Absolute Difference Unsigned Halfword
vabsduw : Vector Absolute Difference Unsigned Word
05: vcmpnezb[.] : Vector Compare Not Equal or Zero Byte
vcmpnezh[.] : Vector Compare Not Equal or Zero Halfword
vcmpnezw[.] : Vector Compare Not Equal or Zero Word
06: vslv : Vector Shift Left Variable
07: vsrv : Vector Shift Right Variable
08: extswsli : Extend Sign Word & Shift Left Immediate
Both part1 and part2 pushed here: https://github.com/nikunjad/qemu/tree/p9-tcg
Changelog:
v1:
* vabsu*: drop abs() and do explicit operation
* vcmpnez*: introduce etype to avoid widening/truncating
* extswsli: drop the condition check
v0:
* Introduce helpers for ISA300 ops
* vabsdu*: drop etype from implementation
* vcmpnez*: collapse the switch case
* vsrv: use reverse traversal to get rid of temporary array
* Include divd/w in this series, as part1 mostly is pushed.
Nikunj A Dadhania (3):
target-ppc: implement branch-less divw[o][.]
target-ppc: implement branch-less divd[o][.]
target-ppc: add extswsli[.] instruction
Sandipan Das (2):
target-ppc: add dtstsfi[q] instructions
target-ppc: add vabsdu[b,h,w] instructions
Swapnil Bokade (1):
target-ppc: add vcmpnez[b,h,w][.] instructions
Vivek Andrew Sha (2):
target-ppc: add vslv instruction
target-ppc: add vsrv instruction
target-ppc/dfp_helper.c | 35 ++++++++++++
target-ppc/helper.h | 13 +++++
target-ppc/int_helper.c | 91 +++++++++++++++++++++++++++++
target-ppc/translate.c | 124 +++++++++++++++++++++++++---------------
target-ppc/translate/dfp-impl.c | 20 +++++++
target-ppc/translate/dfp-ops.c | 14 +++++
target-ppc/translate/vmx-impl.c | 14 +++++
target-ppc/translate/vmx-ops.c | 20 ++++++-
8 files changed, 281 insertions(+), 50 deletions(-)
--
2.7.4
