On Fri, Jun 24, 2016 at 07:55:33AM +0200, Gerd Hoffmann wrote: > On Do, 2016-06-23 at 19:38 +0300, Michael S. Tsirkin wrote: > > On Thu, Jun 23, 2016 at 10:40:03AM +0200, Gerd Hoffmann wrote: > > > Hi, > > > > > > > > Well the crash of guest phys bits > host phys bits, should be easy to > > > > > reproduce by booting a 65GB guest on a 64GB RAM + 2GB swap host with > > > > > 36 host phys bits using the upstream qemu that forces the guest phys > > > > > bits to 40. > > > > > > > > So you supply more RAM than host can address, and guest crashes? > > > > > > Yep. The only reason we don't see this happening in practice is that > > > it's probably next to impossible to find a machine which has (a) only 36 > > > physical address lines and (b) allows to plug that much RAM. > > > > > > > Why are we worried about it? > > > > > > It's more a issue with pci ressources. In theory seabios/edk2 could go > > > figure how big the physical address space is, then map 64bit pci bars as > > > high as possible, thereby making stuff like etc/reserved-memory-end in > > > fw_cfg unnecessary. > > > > > > But with qemu saying 40 phys bits are available even if they are not > > > this approach isn't going to fly ... > > > > > > cheers, > > > Gerd > > > > Nah, x86 guests really need to go by _CRS. > > Yep, we can implement the "soft-phys-bits" that way.
The advantage being no guest changes are necessary. Guests already use _CRS. > > bios doesn't want to parse that > > so it can go by some fw cfg file instead. > > firmware can't use it anyway because the firmware first maps the bars, > the loads acpi tables (while qemu generates _CRS entries according to > the bios mappings). > > > Going by phys bits won't work on old qemu so I don't believe it's > > practical. > > Indeed, so I guess we'll have to stick to the current approach of > mapping 64bit bars above ram (or etc/reserved-memory-end if present). > > cheers, > Gerd
