On Tue, Jul 13, 2010 at 02:05:51PM -0600, Cam Macdonell wrote: > >> > Seabios completely ignore the 64-bitness of the BAR. ?Looks like it also > >> > thinks the second half of the BAR is an I/O region instead of memory > >> > (hence > >> > the c200, that's part of the pci portio region. > > > > I've sent the patches to address it. But they haven't been merged yet. > > seabios doesn't map BARs beyond 4GB. > > If bar is mapped beyond 4GB, guest BIOS does it. > > Have those patches been merged yet?
They have been merged into seabios upstream now. qemu seabios fork hasn't pulled for a while, though. > > To see how seabios works, it would help to increase CONFIG_DEBUG_LEVEL > > in config.h of seabios > > Where does the output from seabios end up? Inside dmesg? It outputs them to the serial console which qemu emulates. seabios is out of kernel control, so dmesg doesn't show it. > >> pci_read_config: (val) 0x0 <- 0x1c (addr) > >> pci_write_config: (val) 0x0 -> 0x1c (addr) > >> pci_read_config: (val) 0xffffffff <- 0x1c (addr) > >> pci_write_config: (val) 0x0 -> 0x1c (addr) > >> pci_read_config: (val) 0x0 <- 0x1c (addr) > >> pci_write_config: (val) 0x0 -> 0x1c (addr) > > > > seabios BAR3. Not sure how it is mapped from this > > message. > > Isn't the BAR3 from the fact that a 64-bit BAR would use both BAR2 and > BAR3 to store all 64-bits? Yes. Seabios misbehaves. 64bit bar is(was) a missing feature. -- yamahata
