On 06/01/2016 11:49 AM, Pranith Kumar wrote:
On Tue, May 31, 2016 at 4:27 PM, Richard Henderson <r...@twiddle.net> wrote:
On 05/31/2016 11:39 AM, Pranith Kumar wrote:
+ case INDEX_op_mb:
+ tcg_out_mb(s);
You need to look at the barrier type and DTRT. In particular, the Linux
smp_rmb and smp_wmb types need not emit any code.
These are converted to 'lfence' and 'sfence' instructions. Based on
the target backend, I think we still need to emit barrier
instructions. For example, if target backend is ARMv7 we need to emit
'dmb' instruction for both x86 fence instructions. I am not sure why
they do not emit any code?
Because x86 has a strong memory model.
It does not require barriers to keep normal loads and stores in order. The
primary reason for the *fence instructions is to order the "non-temporal"
memory operations that are part of the SSE instruction set, which we're not
using at all.
This is why you'll find
/*
* Because of the strongly ordered storage model, wmb() and rmb() are nops
* here (a compiler barrier only). QEMU doesn't do accesses to write-combining
* qemu memory or non-temporal load/stores from C code.
*/
#define smp_wmb() barrier()
#define smp_rmb() barrier()
for x86 and s390.
r~
