On 02/06/16 00:35, Richard Henderson wrote: > On 06/01/2016 11:43 AM, Pranith Kumar wrote: >> All we want to do here is map a barrier instruction from guest to a >> barrier instruction on hist. This mapping is 1:1 if the host has >> barrier instructions with matching semantics. Otherwise we generate a >> multi-op instruction sequence. Some examples are: load acquire(ldar) >> on ARM64 guest will map to dmb+load on ARMv7 target, store >> fence(sfence) on x86 guest will map to dmb on ARMv7 target. > > Perhaps we should model this like the Sparc membar instruction, with > individual bits for all combinations of Load x Store. One can then > describe exactly what the target semantics are for each barrier.
Seconded. Given that we don't support Alpha host we can ignore its unique "Dependent loads reordered" feature. I suppose we're not going to add Alpha host support :) Kind regards, Sergey
