On Sun, May 29, 2016 at 11:21:35AM +0300, David Kiarie wrote:
[...]
> >> +
> >> +/* Programming format for MSI/MSI-X addresses */
> >> +union VTD_IR_MSIAddress {
> >> + struct {
> >> + uint8_t __not_care:2;
> >> + uint8_t index_h:1; /* Interrupt index bit 15 */
> >> + uint8_t sub_valid:1; /* SHV: Sub-Handle Valid bit */
> >> + uint8_t int_mode:1; /* Interrupt format */
> >> + uint16_t index_l:15; /* Interrupt index bit 14-0 */
> >> + uint16_t __head:12; /* Should always be: 0x0fee */
> >> + } QEMU_PACKED;
> >> + uint32_t data;
> >> +};
> >
> > In a recent discussion, it was brought to my attention that you might
> > have a problem with bitfields when the host cpu is not x86. Have you
> > considered this ?
>
> In a case when say the host cpu is little endian.
I assume you mean when host cpu is big endian. x86 was little endian,
and I was testing on x86.
I think you are right. I should do conditional byte swap for all
uint{16/32/64} cases within the fields. For example, index_l field in
above VTD_IR_MSIAddress. And there are several other cases that need
special treatment in the patchset. Will go over and fix corresponding
issues in next version.
Thanks!
-- peterx
