This is to prepare for the ENET Gb device of the i.MX6.
Signed-off-by: Jean-Christophe Dubois <j...@tribudubois.net>
---
Changes since v1:
* Not present on v1.
Changes since v2:
* The patch was split in 2 parts:
- a "port" to a reg array based device (this patch).
- the addition of the Gb support (next patch).
Changes since v3:
* Small fix patches were extracted from this patch (see previous 3
patches)
* Reset logic through ECR was fixed.
* TDAR/RDAR behavior was fixed.
hw/net/imx_fec.c | 396
++++++++++++++++++++++++++---------------------
include/hw/net/imx_fec.h | 55 ++++---
2 files changed, 258 insertions(+), 193 deletions(-)
diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c
index 87e3c87..565b4a3 100644
--- a/hw/net/imx_fec.c
+++ b/hw/net/imx_fec.c
@@ -52,30 +52,75 @@
} \
} while (0)
+static const char *imx_fec_reg_name(IMXFECState *s, uint32_t index)
+{
+ static char tmp[20];
+
+ switch (index) {
+ case ENET_EIR:
+ return "EIR";
+ case ENET_EIMR:
+ return "EIMR";
+ case ENET_RDAR:
+ return "RDAR";
+ case ENET_TDAR:
+ return "TDAR";
+ case ENET_ECR:
+ return "ECR";
+ case ENET_MMFR:
+ return "MMFR";
+ case ENET_MSCR:
+ return "MSCR";
+ case ENET_MIBC:
+ return "MIBC";
+ case ENET_RCR:
+ return "RCR";
+ case ENET_TCR:
+ return "TCR";
+ case ENET_PALR:
+ return "PALR";
+ case ENET_PAUR:
+ return "PAUR";
+ case ENET_OPD:
+ return "OPD";
+ case ENET_IAUR:
+ return "IAUR";
+ case ENET_IALR:
+ return "IALR";
+ case ENET_GAUR:
+ return "GAUR";
+ case ENET_GALR:
+ return "GALR";
+ case ENET_TFWR:
+ return "TFWR";
+ case ENET_RDSR:
+ return "RDSR";
+ case ENET_TDSR:
+ return "TDSR";
+ case ENET_MRBR:
+ return "MRBR";
+ case ENET_FRBR:
+ return "FRBR";
+ case ENET_FRSR:
+ return "FRSR";
+ case ENET_MIIGSK_CFGR:
+ return "MIIGSK_CFGR";
+ case ENET_MIIGSK_ENR:
+ return "MIIGSK_ENR";
+ default:
+ sprintf(tmp, "index %d", index);
+ return tmp;
+ }
+}
+
static const VMStateDescription vmstate_imx_fec = {
.name = TYPE_IMX_FEC,
- .version_id = 1,
- .minimum_version_id = 1,
+ .version_id = 2,
+ .minimum_version_id = 2,
.fields = (VMStateField[]) {
- VMSTATE_UINT32(irq_state, IMXFECState),
- VMSTATE_UINT32(eir, IMXFECState),
- VMSTATE_UINT32(eimr, IMXFECState),
- VMSTATE_UINT32(rx_enabled, IMXFECState),
+ VMSTATE_UINT32_ARRAY(regs, IMXFECState, ENET_MAX),
VMSTATE_UINT32(rx_descriptor, IMXFECState),
VMSTATE_UINT32(tx_descriptor, IMXFECState),
- VMSTATE_UINT32(ecr, IMXFECState),
- VMSTATE_UINT32(mmfr, IMXFECState),
- VMSTATE_UINT32(mscr, IMXFECState),
- VMSTATE_UINT32(mibc, IMXFECState),
- VMSTATE_UINT32(rcr, IMXFECState),
- VMSTATE_UINT32(tcr, IMXFECState),
- VMSTATE_UINT32(tfwr, IMXFECState),
- VMSTATE_UINT32(frsr, IMXFECState),
- VMSTATE_UINT32(erdsr, IMXFECState),
- VMSTATE_UINT32(etdsr, IMXFECState),
- VMSTATE_UINT32(emrbr, IMXFECState),
- VMSTATE_UINT32(miigsk_cfgr, IMXFECState),
- VMSTATE_UINT32(miigsk_enr, IMXFECState),
VMSTATE_UINT32(phy_status, IMXFECState),
VMSTATE_UINT32(phy_control, IMXFECState),
@@ -251,15 +296,13 @@ static void imx_fec_write_bd(IMXFECBufDesc *bd,
dma_addr_t addr)
static void imx_fec_update(IMXFECState *s)
{
- uint32_t active;
- uint32_t changed;
-
- active = s->eir & s->eimr;
- changed = active ^ s->irq_state;
- if (changed) {
- qemu_set_irq(s->irq, active);
+ if (s->regs[ENET_EIR] & s->regs[ENET_EIMR]) {
+ FEC_PRINTF("interrupt raised\n");
+ qemu_set_irq(s->irq, 1);
+ } else {
+ FEC_PRINTF("interrupt lowered\n");
+ qemu_set_irq(s->irq, 0);
}
- s->irq_state = active;
}
static void imx_fec_do_tx(IMXFECState *s)
@@ -283,7 +326,7 @@ static void imx_fec_do_tx(IMXFECState *s)
len = bd.length;
if (frame_size + len > FEC_MAX_FRAME_SIZE) {
len = FEC_MAX_FRAME_SIZE - frame_size;
- s->eir |= FEC_INT_BABT;
+ s->regs[ENET_EIR] |= FEC_INT_BABT;
}
dma_memory_read(&address_space_memory, bd.data, ptr, len);
ptr += len;
@@ -293,17 +336,17 @@ static void imx_fec_do_tx(IMXFECState *s)
qemu_send_packet(qemu_get_queue(s->nic), frame, len);
ptr = frame;
frame_size = 0;
- s->eir |= FEC_INT_TXF;
+ s->regs[ENET_EIR] |= FEC_INT_TXF;
}
- s->eir |= FEC_INT_TXB;
+ s->regs[ENET_EIR] |= FEC_INT_TXB;
bd.flags &= ~FEC_BD_R;
/* Write back the modified descriptor. */
imx_fec_write_bd(&bd, addr);
/* Advance to the next descriptor. */
if ((bd.flags & FEC_BD_W) != 0) {
- addr = s->etdsr;
+ addr = s->regs[ENET_TDSR];
} else {
- addr += 8;
+ addr += sizeof(bd);
}
}
@@ -315,7 +358,7 @@ static void imx_fec_do_tx(IMXFECState *s)
static void imx_fec_enable_rx(IMXFECState *s)
{
IMXFECBufDesc bd;
- uint32_t tmp;
+ bool tmp;
imx_fec_read_bd(&bd, s->rx_descriptor);
@@ -323,11 +366,11 @@ static void imx_fec_enable_rx(IMXFECState *s)
if (!tmp) {
FEC_PRINTF("RX buffer full\n");
- } else if (!s->rx_enabled) {
+ } else if (!s->regs[ENET_RDAR]) {
qemu_flush_queued_packets(qemu_get_queue(s->nic));
}
- s->rx_enabled = tmp;
+ s->regs[ENET_RDAR] = tmp ? ENET_RDAR_RDAR : 0;
}
static void imx_fec_reset(DeviceState *d)
@@ -335,18 +378,26 @@ static void imx_fec_reset(DeviceState *d)
IMXFECState *s = IMX_FEC(d);
/* Reset the FEC */
- s->eir = 0;
- s->eimr = 0;
- s->rx_enabled = 0;
- s->ecr = 0xf0000000;
- s->mscr = 0;
- s->mibc = 0xc0000000;
- s->rcr = 0x05ee0001;
- s->tcr = 0;
- s->tfwr = 0;
- s->frsr = 0x500;
- s->miigsk_cfgr = 0;
- s->miigsk_enr = 0x6;
+ memset(s->regs, 0, sizeof(s->regs));
+ s->regs[ENET_ECR] = 0xf0000000;
+ s->regs[ENET_MIBC] = 0xc0000000;
+ s->regs[ENET_RCR] = 0x05ee0001;
+ s->regs[ENET_OPD] = 0x00010000;
+
+ s->regs[ENET_PALR] = (s->conf.macaddr.a[0] << 24)
+ | (s->conf.macaddr.a[1] << 16)
+ | (s->conf.macaddr.a[2] << 8)
+ | s->conf.macaddr.a[3];
+ s->regs[ENET_PAUR] = (s->conf.macaddr.a[4] << 24)
+ | (s->conf.macaddr.a[5] << 16)
+ | 0x8808;
+
+ s->regs[ENET_FRBR] = 0x00000600;
+ s->regs[ENET_FRSR] = 0x00000500;
+ s->regs[ENET_MIIGSK_ENR] = 0x00000006;
+
+ s->rx_descriptor = 0;
+ s->tx_descriptor = 0;
/* We also reset the PHY */
phy_reset(s);
@@ -354,183 +405,180 @@ static void imx_fec_reset(DeviceState *d)
static uint64_t imx_fec_read(void *opaque, hwaddr addr, unsigned
size)
{
+ uint32_t value = 0;
IMXFECState *s = IMX_FEC(opaque);
-
- FEC_PRINTF("reading from @ 0x%" HWADDR_PRIx "\n", addr);
-
- switch (addr & 0x3ff) {
- case 0x004:
- return s->eir;
- case 0x008:
- return s->eimr;
- case 0x010:
- return s->rx_enabled ? (1 << 24) : 0; /* RDAR */
- case 0x014:
- return 0; /* TDAR */
- case 0x024:
- return s->ecr;
- case 0x040:
- return s->mmfr;
- case 0x044:
- return s->mscr;
- case 0x064:
- return s->mibc; /* MIBC */
- case 0x084:
- return s->rcr;
- case 0x0c4:
- return s->tcr;
- case 0x0e4: /* PALR */
- return (s->conf.macaddr.a[0] << 24)
- | (s->conf.macaddr.a[1] << 16)
- | (s->conf.macaddr.a[2] << 8)
- | s->conf.macaddr.a[3];
- break;
- case 0x0e8: /* PAUR */
- return (s->conf.macaddr.a[4] << 24)
- | (s->conf.macaddr.a[5] << 16)
- | 0x8808;
- case 0x0ec:
- return 0x10000; /* OPD */
- case 0x118:
- return 0;
- case 0x11c:
- return 0;
- case 0x120:
- return 0;
- case 0x124:
- return 0;
- case 0x144:
- return s->tfwr;
- case 0x14c:
- return 0x600;
- case 0x150:
- return s->frsr;
- case 0x180:
- return s->erdsr;
- case 0x184:
- return s->etdsr;
- case 0x188:
- return s->emrbr;
- case 0x300:
- return s->miigsk_cfgr;
- case 0x308:
- return s->miigsk_enr;
+ uint32_t index = addr >> 2;
+
+ switch (index) {
+ case ENET_EIR:
+ case ENET_EIMR:
+ case ENET_RDAR:
+ case ENET_TDAR:
+ case ENET_ECR:
+ case ENET_MMFR:
+ case ENET_MSCR:
+ case ENET_MIBC:
+ case ENET_RCR:
+ case ENET_TCR:
+ case ENET_PALR:
+ case ENET_PAUR:
+ case ENET_OPD:
+ case ENET_IAUR:
+ case ENET_IALR:
+ case ENET_GAUR:
+ case ENET_GALR:
+ case ENET_TFWR:
+ case ENET_RDSR:
+ case ENET_TDSR:
+ case ENET_MRBR:
+ case ENET_FRBR:
+ case ENET_FRSR:
+ case ENET_MIIGSK_CFGR:
+ case ENET_MIIGSK_ENR:
+ value = s->regs[index];
+ break;
default:
- qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad address at
offset 0x%"
- HWADDR_PRIx "\n", TYPE_IMX_FEC, __func__, addr);
- return 0;
+ qemu_log_mask(LOG_GUEST_ERROR, "[%s]%s: Bad register at
offset 0x%"
+ PRIx32 "\n", TYPE_IMX_FEC, __func__, index * 4);
+ break;
}
+
+ FEC_PRINTF("reg[%s] => 0x%" PRIx32 "\n", imx_fec_reg_name(s,
index),
+ value);
+
+ return value;
}
static void imx_fec_write(void *opaque, hwaddr addr,
uint64_t value, unsigned size)
{
IMXFECState *s = IMX_FEC(opaque);
+ uint32_t index = addr >> 2;
- FEC_PRINTF("writing 0x%08x @ 0x%" HWADDR_PRIx "\n",
(int)value, addr);
+ FEC_PRINTF("reg[%s] <= 0x%" PRIx32 "\n", imx_fec_reg_name(s,
index),
+ (uint32_t)value);
- switch (addr & 0x3ff) {
- case 0x004: /* EIR */
- s->eir &= ~value;
+ switch (index) {
+ case ENET_EIR:
+ s->regs[index] &= ~value;
break;
- case 0x008: /* EIMR */
- s->eimr = value;
+ case ENET_EIMR:
+ s->regs[index] = value;
break;
- case 0x010: /* RDAR */
- if ((s->ecr & FEC_EN) && !s->rx_enabled) {
- imx_fec_enable_rx(s);
+ case ENET_RDAR:
+ if (s->regs[ENET_ECR] & FEC_EN) {
+ if (!s->regs[index]) {
+ s->regs[index] = ENET_RDAR_RDAR;
+ imx_fec_enable_rx(s);
+ }
+ } else {
+ s->regs[index] = 0;
}
break;
- case 0x014: /* TDAR */
- if (s->ecr & FEC_EN) {
+ case ENET_TDAR:
+ if (s->regs[ENET_ECR] & FEC_EN) {
+ s->regs[index] = ENET_TDAR_TDAR;
imx_fec_do_tx(s);
}
+ s->regs[index] = 0;
break;
- case 0x024: /* ECR */
- s->ecr = value;
+ case ENET_ECR:
if (value & FEC_RESET) {
- imx_fec_reset(DEVICE(s));
+ return imx_fec_reset(DEVICE(s));
}
- if ((s->ecr & FEC_EN) == 0) {
- s->rx_enabled = 0;
+ s->regs[index] = value;
+ if ((s->regs[index] & FEC_EN) == 0) {
+ s->regs[ENET_RDAR] = 0;
+ s->rx_descriptor = s->regs[ENET_RDSR];
+ s->regs[ENET_TDAR] = 0;
+ s->tx_descriptor = s->regs[ENET_TDSR];
