On Fri, Jan 15, 2016 at 6:36 AM, Peter Maydell <peter.mayd...@linaro.org> wrote: > On 12 January 2016 at 22:39, Alistair Francis > <alistair.fran...@xilinx.com> wrote: >> The Xilinx ZynqMP SoC and EP108 board supports three memory regions: >> - A 2GB region starting at 0 >> - A 32GB region starting at 32GB >> - A 256GB region starting at 768GB >> >> This patch adds support for the first two memory regions, which is >> automatically created based on the size specified by the QEMU memory >> command line argument. >> >> On hardware the physical memory region is one continuous region, it is then >> mapped into the three different regions by the DDRC. As we don't model the >> DDRC this is done at startup by QEMU. The board creates the memory region and >> then passes that memory region to the SoC. The SoC then maps the memory >> regions. >> >> Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> >> Reviewed-by: Peter Crosthwaite <crosthwaite.pe...@gmail.com> >> --- >> V5: >> - Fix compilation on 32-bit host issue >> V4: >> - Small fixes >> - Localisation of ram_size >> V3: >> - Assert on the RAM sizes >> - Remove ram_size property >> - General fixes >> V2: >> - Create one continuous memory region and pass it to the SoC > > > > Applied to target-arm.next, thanks.
Thanks! Alistair > > -- PMM >
