Signed-off-by: Andrew Jones <drjo...@redhat.com>
---
target-arm/cpu.h | 45 +++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 45 insertions(+)
diff --git a/target-arm/cpu.h b/target-arm/cpu.h
index 815fef8a30663..9231a9ff3b9c2 100644
--- a/target-arm/cpu.h
+++ b/target-arm/cpu.h
@@ -863,6 +863,51 @@ enum arm_cpu_mode {
#define ARM_IWMMXT_wCGR2 10
#define ARM_IWMMXT_wCGR3 11
+/* AArch64 to AArch32 register mappings */
+#define compat_fp_usr xregs[11]
+#define compat_sp_usr xregs[13]
+#define compat_lr_usr xregs[14]
+#define compat_sp_hyp xregs[15]
+#define compat_lr_irq xregs[16]
+#define compat_sp_irq xregs[17]
+#define compat_lr_svc xregs[18]
+#define compat_sp_svc xregs[19]
+#define compat_lr_abt xregs[20]
+#define compat_sp_abt xregs[21]
+#define compat_lr_und xregs[22]
+#define compat_sp_und xregs[23]
+#define compat_r8_fiq xregs[24]
+#define compat_r9_fiq xregs[25]
+#define compat_r10_fiq xregs[26]
+#define compat_r11_fiq xregs[27]
+#define compat_r12_fiq xregs[28]
+#define compat_sp_fiq xregs[29]
+#define compat_lr_fiq xregs[30]
+
+static inline uint64_t aarch64_compat_sp(CPUARMState *env)
+{
+ uint32_t mode = env->uncached_cpsr & CPSR_M;
+
+ switch (mode) {
+ case ARM_CPU_MODE_USR:
+ case ARM_CPU_MODE_SYS:
+ return env->compat_sp_usr;
+ case ARM_CPU_MODE_FIQ:
+ return env->compat_sp_fiq;
+ case ARM_CPU_MODE_IRQ:
+ return env->compat_sp_irq;
+ case ARM_CPU_MODE_SVC:
+ return env->compat_sp_svc;
+ case ARM_CPU_MODE_ABT:
+ return env->compat_sp_abt;
+ case ARM_CPU_MODE_HYP:
+ return env->compat_sp_hyp;
+ case ARM_CPU_MODE_UND:
+ return env->compat_sp_und;
+ }
+ g_assert_not_reached();
+}
+
/* If adding a feature bit which corresponds to a Linux ELF
* HWCAP bit, remember to update the feature-bit-to-hwcap
* mapping in linux-user/elfload.c:get_elf_hwcap().
--
2.4.3
