All, Second revision of ARMv7-M exception handling patchset, which now adds MPU support (as well as can be done).
Parts of this series are informed by the previous work of Alex Zuepke. This time I have access to a EK-TM4C1294XL eval board (cortex-m4f), and have done some cross-checks using test programs of my own[1]. There are differences in some corner cases, but mostly agreement (certainly better than before). This series attempts to fix the exception masking and priority escalation behavour, and in the process removes the dependence of the NVIC on the shared GIC code. It also fills out some of the missing fault reporting registers. The CCR register is also added, mainly to implement the STACKALIGN bit. I've also made an attempt on USERSETMPEND. BFHFNMIGN, DIV_0_TRP, UNALIGN_TRP remain unimplemnted. Additional checks are added to do_v7m_exception_exit() to capture the faults which should arise when the guest stack gets out of sync with the CPU's state. In cross-checking with a real device I also found that the behavour of CONTROL bit 1 wasn't as spec'd in exception handlers. I also "discovered" that many v7-M targets don't implement all 8 bits of the priority registers (the TM4C1294 only has 3). So I've added a Property to allow this to be set appropriately. This led me to make some changes to allow board code to actually set this Property, which entailed splitting armv7m_init() in two parts, and associated changes to the stellaris and stm32f205 boards. I'm not completely happy with the level of compatibility with the MPU. For my own purposes it's good enough as I can make special builds. However, the additional alignment and size restrictions imposed by the common TLB and 1024 page size will probably break most unmodified guests using the MPU. I can't see any way around this short of changes to the TLB code, or a seperate build with TARGET_PAGE_BITS==5. I'm not inclined to undertake either. Should this part of the series be dropped? Michael [1] https://github.com/mdavidsaver/baremetal/tree/qemutest Michael Davidsaver (26): armv7m: MRS/MSR handle unprivileged access armv7m: Undo armv7m.hack armv7m: Explicit error for bad vector table armv7m: additional cpu state for exception handling armv7m: add armv7m_excp_running_prio() armv7m: fix I and F flag handling armv7m: simpler/faster exception start armv7m: rewrite NVIC armv7m: implement CFSR, HFSR, BFAR, and MMFAR armv7m: auto-clear FAULTMASK arm: gic: Remove references to NVIC armv7m: check exception return consistency armv7m: implement CCR armv7m: prevent unprivileged write to STIR armv7m: add MPU to cortex-m3 and cortex-m4 armv7m: add some mpu debugging prints armv7m: mpu background miss is perm fault armv7m: update base region policy armv7m: mpu not allowed to map exception return codes armv7m: observable initial register state armv7m: CONTROL<1> handling armv7m: priority field mask qom: add cpu_generic_init_unrealized() armv7m: split armv7m_init in two parts armv7m: remove extra cpu_reset() armv7m: decide whether faults are MemManage or BusFault hw/arm/armv7m.c | 60 ++- hw/arm/stellaris.c | 7 +- hw/arm/stm32f205_soc.c | 6 +- hw/intc/arm_gic.c | 14 +- hw/intc/arm_gic_common.c | 23 +- hw/intc/armv7m_nvic.c | 1037 +++++++++++++++++++++++++++++++++++++--------- hw/intc/gic_internal.h | 7 +- include/hw/arm/arm.h | 4 +- include/qom/cpu.h | 12 + qom/cpu.c | 23 +- target-arm/cpu-qom.h | 6 + target-arm/cpu.c | 61 ++- target-arm/cpu.h | 17 +- target-arm/helper.c | 346 ++++++++++++---- target-arm/machine.c | 11 +- 15 files changed, 1252 insertions(+), 382 deletions(-) -- 2.1.4
