On 11/17/2015 04:40 AM, Max Reitz wrote:
- tcg_gen_mulu2_i64(cpu_regs[s->vex_v], cpu_regs[reg],
- cpu_T[0], cpu_regs[R_EDX]);
+ tcg_gen_op3_i64(INDEX_op_mul_i64, cpu_regs[s->vex_v],
+ cpu_T[0], cpu_regs[R_EDX]);
+ if (TCG_TARGET_HAS_muluh_i64) {
+ tcg_gen_op3_i64(INDEX_op_muluh_i64, cpu_regs[reg],
+ cpu_T[0], cpu_regs[R_EDX]);
+ } else {
+ gen_helper_muluh_i64(cpu_regs[reg],
+ cpu_T[0], cpu_regs[R_EDX]);
+ }
This is not the correct fix.
I do see the operand write order present in the pseudo-code of the intel
manual. So that part of the diagnosis is fine.
But the correct solution is to put the outputs of tcg_gen_mulu2 into
temporaries (cpu_T[0] and cpu_T[1]) and then afterward write back the results
into the architectual registers in the correct order.
r~
