On 09/28/2015 03:06 PM, gang.chen.5...@gmail.com wrote:
From: Chen Gang <gang.chen.5...@gmail.com>Acording to the __longjmp tilegx libc implementation, and reference from tilegx ISA document, we can left iret instruction empty. The related code is below: ENTRY (__longjmp) FEEDBACK_ENTER(__longjmp) #define RESTORE(r) { LD r, r0 ; ADDI_PTR r0, r0, REGSIZE } FOR_EACH_CALLEE_SAVED_REG(RESTORE) { LD r2, r0 ; retrieve ICS bit from jmp_buf movei r3, 1 CMPEQI r0, r1, 0 } { mtspr INTERRUPT_CRITICAL_SECTION, r3 shli r2, r2, SPR_EX_CONTEXT_0_1__ICS_SHIFT } { mtspr EX_CONTEXT_0_0, lr ori r2, r2, RETURN_PL } { or r0, r1, r0 mtspr EX_CONTEXT_0_1, r2 } iret jrp lr So can let busybox sh run correctly. Signed-off-by: Chen Gang <gang.chen.5...@gmail.com> --- target-tilegx/cpu.h | 2 ++ target-tilegx/translate.c | 8 +++++++- 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/target-tilegx/cpu.h b/target-tilegx/cpu.h index 4b05cd2..02e1a18 100644 --- a/target-tilegx/cpu.h +++ b/target-tilegx/cpu.h @@ -54,6 +54,8 @@ enum { TILEGX_SPR_CRITICAL_SEC = 1, TILEGX_SPR_SIM_CONTROL = 2, TILEGX_SPR_EX_CONTEXT_1 = 3, + TILEGX_SPR_EX_CONTEXT_0_0 = 4, + TILEGX_SPR_EX_CONTEXT_0_1 = 5,
Don't add spr's you're not going to use. r~
