On 19 September 2015 at 07:15, Edgar E. Iglesias
<edgar.igles...@gmail.com> wrote:
> From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
>
> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
> ---
> target-arm/cpu.h | 1 +
> target-arm/helper.c | 7 +++++++
> 2 files changed, 8 insertions(+)
>
> diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> index 1b80516..e7694a5 100644
> --- a/target-arm/cpu.h
> +++ b/target-arm/cpu.h
> @@ -280,6 +280,7 @@ typedef struct CPUARMState {
> };
> uint64_t far_el[4];
> };
> + uint64_t hpfar_el2;
> union { /* Translation result. */
> struct {
> uint64_t _unused_par_0;
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 12ea88f..b709582 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -3221,6 +3221,9 @@ static const ARMCPRegInfo el3_no_el2_cp_reginfo[] = {
> { .name = "CNTHP_CTL_EL2", .state = ARM_CP_STATE_BOTH,
> .opc0 = 3, .opc1 = 4, .crn = 14, .crm = 2, .opc2 = 1,
> .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
> + .access = PL2_RW, .type = ARM_CP_CONST, .resetvalue = 0 },
> REGINFO_SENTINEL
> };
>
> @@ -3442,6 +3445,10 @@ static const ARMCPRegInfo el2_cp_reginfo[] = {
> .resetvalue = 0,
> .writefn = gt_hyp_ctl_write, .raw_writefn = raw_write },
> #endif
> + { .name = "HPFAR_EL2", .state = ARM_CP_STATE_BOTH,
> + .opc0 = 3, .opc1 = 4, .crn = 6, .crm = 0, .opc2 = 4,
> + .access = PL2_RW,
> + .fieldoffset = offsetof(CPUARMState, cp15.hpfar_el2) },
> REGINFO_SENTINEL
> }
Shouldn't these have the accessfn for "no access from 32-bit EL3
if SCR.NS is 0" ?
thanks
-- PMM
