Bit 15 of the PHY Specific Status Register is reserved and should remain 0. Fix the reset value to ensure that the 15th bit is not set.
Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com> --- http://www.marvell.com/transceivers/assets/Marvell-88E3016-Fast-Ethernet.pdf hw/net/cadence_gem.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 494a346..1127223 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -951,7 +951,7 @@ static void gem_phy_reset(CadenceGEMState *s) s->phy_regs[PHY_REG_1000BTSTAT] = 0x7C00; s->phy_regs[PHY_REG_EXTSTAT] = 0x3000; s->phy_regs[PHY_REG_PHYSPCFC_CTL] = 0x0078; - s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0xBC00; + s->phy_regs[PHY_REG_PHYSPCFC_ST] = 0x7C00; s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL] = 0x0C60; s->phy_regs[PHY_REG_LED] = 0x4100; s->phy_regs[PHY_REG_EXT_PHYSPCFC_CTL2] = 0x000A; -- 1.7.1
