Signed-off-by: Emilio G. Cota <c...@braap.org>
---
cpu-exec.c | 9 ++++++---
exec.c | 2 +-
hw/openrisc/cputimer.c | 2 +-
qom/cpu.c | 4 ++--
target-arm/helper-a64.c | 2 +-
target-arm/helper.c | 2 +-
target-i386/helper.c | 2 +-
target-i386/seg_helper.c | 14 +++++++-------
target-i386/svm_helper.c | 4 ++--
target-openrisc/interrupt_helper.c | 2 +-
target-openrisc/sys_helper.c | 2 +-
target-ppc/excp_helper.c | 8 ++++----
target-ppc/helper_regs.h | 2 +-
target-s390x/helper.c | 2 +-
target-unicore32/softmmu.c | 2 +-
translate-all.c | 4 ++--
16 files changed, 33 insertions(+), 30 deletions(-)
diff --git a/cpu-exec.c b/cpu-exec.c
index 2b9a447..fd57b9c 100644
--- a/cpu-exec.c
+++ b/cpu-exec.c
@@ -463,12 +463,14 @@ int cpu_exec(CPUState *cpu)
interrupt_request &= ~CPU_INTERRUPT_SSTEP_MASK;
}
if (interrupt_request & CPU_INTERRUPT_DEBUG) {
- cpu->interrupt_request &= ~CPU_INTERRUPT_DEBUG;
+ atomic_and(&cpu->interrupt_request,
+ ~CPU_INTERRUPT_DEBUG);
cpu->exception_index = EXCP_DEBUG;
cpu_loop_exit(cpu);
}
if (interrupt_request & CPU_INTERRUPT_HALT) {
- cpu->interrupt_request &= ~CPU_INTERRUPT_HALT;
+ atomic_and(&cpu->interrupt_request,
+ ~CPU_INTERRUPT_HALT);
cpu->halted = 1;
cpu->exception_index = EXCP_HLT;
cpu_loop_exit(cpu);
@@ -495,7 +497,8 @@ int cpu_exec(CPUState *cpu)
/* Don't use the cached interrupt_request value,
do_interrupt may have updated the EXITTB flag. */
if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) {
- cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB;
+ atomic_and(&cpu->interrupt_request,
+ ~CPU_INTERRUPT_EXITTB);
/* ensure that no TB jump will be modified as
the program flow was changed */
next_tb = 0;
diff --git a/exec.c b/exec.c
index ff79c3d..edf2236 100644
--- a/exec.c
+++ b/exec.c
@@ -445,7 +445,7 @@ static int cpu_common_post_load(void *opaque, int
version_id)
/* 0x01 was CPU_INTERRUPT_EXIT. This line can be removed when the
version_id is increased. */
- cpu->interrupt_request &= ~0x01;
+ atomic_and(&cpu->interrupt_request, ~0x01);
tlb_flush(cpu, 1);
return 0;
diff --git a/hw/openrisc/cputimer.c b/hw/openrisc/cputimer.c
index 9c54945..2451698 100644
--- a/hw/openrisc/cputimer.c
+++ b/hw/openrisc/cputimer.c
@@ -85,7 +85,7 @@ static void openrisc_timer_cb(void *opaque)
CPUState *cs = CPU(cpu);
cpu->env.ttmr |= TTMR_IP;
- cs->interrupt_request |= CPU_INTERRUPT_TIMER;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_TIMER);
}
switch (cpu->env.ttmr & TTMR_M) {
diff --git a/qom/cpu.c b/qom/cpu.c
index 3841f0d..ac19710 100644
--- a/qom/cpu.c
+++ b/qom/cpu.c
@@ -108,7 +108,7 @@ static void cpu_common_get_memory_mapping(CPUState *cpu,
void cpu_reset_interrupt(CPUState *cpu, int mask)
{
- cpu->interrupt_request &= ~mask;
+ atomic_and(&cpu->interrupt_request, ~mask);
}
void cpu_exit(CPUState *cpu)
@@ -242,7 +242,7 @@ static void cpu_common_reset(CPUState *cpu)
log_cpu_state(cpu, cc->reset_dump_flags);
}
- cpu->interrupt_request = 0;
+ atomic_set(&cpu->interrupt_request, 0);
cpu->current_tb = NULL;
cpu->halted = 0;
cpu->mem_io_pc = 0;
diff --git a/target-arm/helper-a64.c b/target-arm/helper-a64.c
index 08c95a3..05c4ab6 100644
--- a/target-arm/helper-a64.c
+++ b/target-arm/helper-a64.c
@@ -541,6 +541,6 @@ void aarch64_cpu_do_interrupt(CPUState *cs)
aarch64_restore_sp(env, new_el);
env->pc = addr;
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_EXITTB);
}
#endif
diff --git a/target-arm/helper.c b/target-arm/helper.c
index aea5a4b..fc8f5b3 100644
--- a/target-arm/helper.c
+++ b/target-arm/helper.c
@@ -4980,7 +4980,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
}
env->regs[14] = env->regs[15] + offset;
env->regs[15] = addr;
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_EXITTB);
}
diff --git a/target-i386/helper.c b/target-i386/helper.c
index 5480a96..6339832 100644
--- a/target-i386/helper.c
+++ b/target-i386/helper.c
@@ -1232,7 +1232,7 @@ void do_cpu_init(X86CPU *cpu)
*save = *env;
cpu_reset(cs);
- cs->interrupt_request = sipi;
+ atomic_set(&cs->interrupt_request, sipi);
memcpy(&env->start_init_save, &save->start_init_save,
offsetof(CPUX86State, end_init_save) -
offsetof(CPUX86State, start_init_save));
diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c
index 8a4271e..2753cc6 100644
--- a/target-i386/seg_helper.c
+++ b/target-i386/seg_helper.c
@@ -1292,7 +1292,7 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
#if !defined(CONFIG_USER_ONLY)
if (interrupt_request & CPU_INTERRUPT_POLL) {
- cs->interrupt_request &= ~CPU_INTERRUPT_POLL;
+ atomic_and(&cs->interrupt_request, ~CPU_INTERRUPT_POLL);
apic_poll_irq(cpu->apic_state);
}
#endif
@@ -1302,17 +1302,17 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
if ((interrupt_request & CPU_INTERRUPT_SMI) &&
!(env->hflags & HF_SMM_MASK)) {
cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0);
- cs->interrupt_request &= ~CPU_INTERRUPT_SMI;
+ atomic_and(&cs->interrupt_request, ~CPU_INTERRUPT_SMI);
do_smm_enter(cpu);
ret = true;
} else if ((interrupt_request & CPU_INTERRUPT_NMI) &&
!(env->hflags2 & HF2_NMI_MASK)) {
- cs->interrupt_request &= ~CPU_INTERRUPT_NMI;
+ atomic_and(&cs->interrupt_request, ~CPU_INTERRUPT_NMI);
env->hflags2 |= HF2_NMI_MASK;
do_interrupt_x86_hardirq(env, EXCP02_NMI, 1);
ret = true;
} else if (interrupt_request & CPU_INTERRUPT_MCE) {
- cs->interrupt_request &= ~CPU_INTERRUPT_MCE;
+ atomic_and(&cs->interrupt_request, ~CPU_INTERRUPT_MCE);
do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0);
ret = true;
} else if ((interrupt_request & CPU_INTERRUPT_HARD) &&
@@ -1323,8 +1323,8 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
!(env->hflags & HF_INHIBIT_IRQ_MASK))))) {
int intno;
cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0);
- cs->interrupt_request &= ~(CPU_INTERRUPT_HARD |
- CPU_INTERRUPT_VIRQ);
+ atomic_and(&cs->interrupt_request, ~(CPU_INTERRUPT_HARD |
+ CPU_INTERRUPT_VIRQ));
intno = cpu_get_pic_interrupt(env);
qemu_log_mask(CPU_LOG_TB_IN_ASM,
"Servicing hardware INT=0x%02x\n", intno);
@@ -1344,7 +1344,7 @@ bool x86_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
qemu_log_mask(CPU_LOG_TB_IN_ASM,
"Servicing virtual hardware INT=0x%02x\n", intno);
do_interrupt_x86_hardirq(env, intno, 1);
- cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
+ atomic_and(&cs->interrupt_request, ~CPU_INTERRUPT_VIRQ);
ret = true;
#endif
}
diff --git a/target-i386/svm_helper.c b/target-i386/svm_helper.c
index f1fabf5..cedc3ef 100644
--- a/target-i386/svm_helper.c
+++ b/target-i386/svm_helper.c
@@ -296,7 +296,7 @@ void helper_vmrun(CPUX86State *env, int aflag, int
next_eip_addend)
if (int_ctl & V_IRQ_MASK) {
CPUState *cs = CPU(x86_env_get_cpu(env));
- cs->interrupt_request |= CPU_INTERRUPT_VIRQ;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_VIRQ);
}
/* maybe we need to inject an event */
@@ -665,7 +665,7 @@ void helper_vmexit(CPUX86State *env, uint32_t exit_code,
uint64_t exit_info_1)
env->hflags &= ~HF_SVMI_MASK;
env->intercept = 0;
env->intercept_exceptions = 0;
- cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ;
+ atomic_and(&cs->interrupt_request, ~CPU_INTERRUPT_VIRQ);
env->tsc_offset = 0;
env->gdt.base = x86_ldq_phys(cs, env->vm_hsave + offsetof(struct vmcb,
diff --git a/target-openrisc/interrupt_helper.c
b/target-openrisc/interrupt_helper.c
index 55a780c..300a980 100644
--- a/target-openrisc/interrupt_helper.c
+++ b/target-openrisc/interrupt_helper.c
@@ -54,5 +54,5 @@ void HELPER(rfe)(CPUOpenRISCState *env)
tlb_flush(cs, 1);
}
#endif
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_EXITTB);
}
diff --git a/target-openrisc/sys_helper.c b/target-openrisc/sys_helper.c
index 53ca6bc..4be72af 100644
--- a/target-openrisc/sys_helper.c
+++ b/target-openrisc/sys_helper.c
@@ -148,7 +148,7 @@ void HELPER(mtspr)(CPUOpenRISCState *env,
env->ttmr = (rb & ~TTMR_IP) | ip;
} else { /* Clear IP bit. */
env->ttmr = rb & ~TTMR_IP;
- cs->interrupt_request &= ~CPU_INTERRUPT_TIMER;
+ atomic_and(&cs->interrupt_request, ~CPU_INTERRUPT_TIMER);
}
cpu_openrisc_timer_update(cpu);
diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c
index b803475..b6e17e9 100644
--- a/target-ppc/excp_helper.c
+++ b/target-ppc/excp_helper.c
@@ -139,7 +139,7 @@ static inline void powerpc_excp(PowerPCCPU *cpu, int
excp_model, int excp)
"Entering checkstop state\n");
}
cs->halted = 1;
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_EXITTB);
}
if (0) {
/* XXX: find a suitable condition to enable the hypervisor mode */
@@ -828,7 +828,7 @@ bool ppc_cpu_exec_interrupt(CPUState *cs, int
interrupt_request)
if (interrupt_request & CPU_INTERRUPT_HARD) {
ppc_hw_interrupt(env);
if (env->pending_interrupts == 0) {
- cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ atomic_and(&cs->interrupt_request, ~CPU_INTERRUPT_HARD);
}
return true;
}
@@ -872,7 +872,7 @@ void helper_store_msr(CPUPPCState *env, target_ulong val)
val = hreg_store_msr(env, val, 0);
if (val != 0) {
cs = CPU(ppc_env_get_cpu(env));
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_EXITTB);
helper_raise_exception(env, val);
}
}
@@ -906,7 +906,7 @@ static inline void do_rfi(CPUPPCState *env, target_ulong
nip, target_ulong msr,
/* No need to raise an exception here,
* as rfi is always the last insn of a TB
*/
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_EXITTB);
}
void helper_rfi(CPUPPCState *env)
diff --git a/target-ppc/helper_regs.h b/target-ppc/helper_regs.h
index 271fddf..3164714 100644
--- a/target-ppc/helper_regs.h
+++ b/target-ppc/helper_regs.h
@@ -85,7 +85,7 @@ static inline int hreg_store_msr(CPUPPCState *env,
target_ulong value,
/* Flush all tlb when changing translation mode */
tlb_flush(cs, 1);
excp = POWERPC_EXCP_NONE;
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_EXITTB);
}
if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
((value ^ env->msr) & (1 << MSR_TGPR)))) {
diff --git a/target-s390x/helper.c b/target-s390x/helper.c
index d887006..f11bd08 100644
--- a/target-s390x/helper.c
+++ b/target-s390x/helper.c
@@ -563,7 +563,7 @@ void s390_cpu_do_interrupt(CPUState *cs)
cs->exception_index = -1;
if (!env->pending_int) {
- cs->interrupt_request &= ~CPU_INTERRUPT_HARD;
+ atomic_and(&cs->interrupt_request, ~CPU_INTERRUPT_HARD);
}
}
diff --git a/target-unicore32/softmmu.c b/target-unicore32/softmmu.c
index 9a3786d..9da5287 100644
--- a/target-unicore32/softmmu.c
+++ b/target-unicore32/softmmu.c
@@ -116,7 +116,7 @@ void uc32_cpu_do_interrupt(CPUState *cs)
/* The PC already points to the proper instruction. */
env->regs[30] = env->regs[31];
env->regs[31] = addr;
- cs->interrupt_request |= CPU_INTERRUPT_EXITTB;
+ atomic_or(&cs->interrupt_request, CPU_INTERRUPT_EXITTB);
}
static int get_phys_addr_ucv2(CPUUniCore32State *env, uint32_t address,
diff --git a/translate-all.c b/translate-all.c
index f07547e..12eaed7 100644
--- a/translate-all.c
+++ b/translate-all.c
@@ -1596,7 +1596,7 @@ static void tcg_handle_interrupt(CPUState *cpu, int mask)
int old_mask;
old_mask = cpu->interrupt_request;
- cpu->interrupt_request |= mask;
+ atomic_or(&cpu->interrupt_request, mask);
/*
* If called from iothread context, wake the target cpu in
@@ -1790,7 +1790,7 @@ void dump_opcount_info(FILE *f, fprintf_function
cpu_fprintf)
void cpu_interrupt(CPUState *cpu, int mask)
{
- cpu->interrupt_request |= mask;
+ atomic_or(&cpu->interrupt_request, mask);
cpu->tcg_exit_req = 1;
}
--
1.9.1
