Public bug reported: In the arm_timer.c, when first reading the load register, I got 0.
... case 0: /* TimerLoad */ ... According to the specification at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html, "The minimum valid value for TimerXLoad is 1". Is the initial value supposed to be 0xffffffff? When the 5th and 7th bit in Control Register are set, RIS and MIS remain 0. But should they be enabled (i.e., 0x1 and 0x1) as both interrupt and timer module are set. Thanks. ** Affects: qemu Importance: Undecided Status: New -- You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/1480562 Title: register values in sp804 timer Status in QEMU: New Bug description: In the arm_timer.c, when first reading the load register, I got 0. ... case 0: /* TimerLoad */ ... According to the specification at http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0271d/index.html, "The minimum valid value for TimerXLoad is 1". Is the initial value supposed to be 0xffffffff? When the 5th and 7th bit in Control Register are set, RIS and MIS remain 0. But should they be enabled (i.e., 0x1 and 0x1) as both interrupt and timer module are set. Thanks. To manage notifications about this bug go to: https://bugs.launchpad.net/qemu/+bug/1480562/+subscriptions
