This patchset enables the TZ support in the GIC for the systems
where we enable TZ support in the CPU. In practice that means
just the "virt" and "vexpress" boards, since all the others
disable the CPU TZ support.
Patch 1 I've already put out on list as a bugfix targeting 2.4.
The main interesting part in this is that we need some special
handling for the case where both the CPU and the GIC have TZ
support but we want to directly boot a kernel in NonSecure
(this only happens with the "virt" board). In this case our
hw/arm/boot.c minimalist bootloader needs to do the work of
configuring the GIC that would normally be done by Secure
firmware before it started the NS kernel. I've opted to do this
by adding a property on the GIC which says "reset yourself as
if you'd been configured by firmware to make all the IRQs NS",
and then set that property from boot.c if appropriate.
The other possible approach would be to have the code that
boot.c runs in the guest do this reconfiguration, but that
would be awkward because we'd need to start both the primary
and secondary CPUs in Secure and have them do the step-down-to-NS
themselves after messing with the GIC. If people strongly prefer
that I can have a go at it, but I'd really rather not :-)
Andreas, I cc'd you in case you wanted to have a look at whether
I got the property-which-can-be-set-after-realize right (patch 2).
thanks
-- PMM
Peter Maydell (5):
hw/intc/arm_gic_common.c: Reset all registers
hw/intc/arm_gic_common: Provide property to make IRQs reset as
NonSecure
hw/arm/boot: Configure secure GIC to make IRQs NS if booting an NS
kernel
hw/cpu/{a15mpcore,a9mpcore}: enable TrustZone in GIC if it is enabled
in CPUs
hw/arm/virt: Enable TZ extensions on the GIC if we are using them
hw/arm/boot.c | 39 ++++++++++++++++++++++
hw/arm/virt.c | 7 ++--
hw/cpu/a15mpcore.c | 13 ++++++++
hw/cpu/a9mpcore.c | 11 ++++++
hw/intc/arm_gic_common.c | 72 +++++++++++++++++++++++++++++++++++++---
include/hw/intc/arm_gic_common.h | 1 +
6 files changed, 137 insertions(+), 6 deletions(-)
--
1.9.1
