On 26/06/2015 18:08, Peter Maydell wrote:
>> > Yeah, ISTR that in some cases you have to wait for other CPUs to
>> > invalidate the TLB before proceeding.  Maybe it's only when you have a
>> > dmb instruction, but it's probably simpler for QEMU to always do it
>> > synchronously.
> Yeah, the ARM architectural requirement here is that the TLB
> operation is complete after a DSB instruction executes. (True for
> any TLB op, not just the all-CPUs ones). NB that we also call
> tlb_flush() from target-arm/ code for some things like "we just
> updated a system register"; some of those have "must take effect
> immediately" semantics.
> 
> In any case, for generic code we have to also consider the
> semantics of non-ARM guests...

I think it would be okay to make this an ARM-specific thing.  In most
other architectures that I know of, TLB shootdowns are done in software
thorough IPI.

Paolo

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