On Thu, Jun 4, 2015 at 11:41 PM, Alistair Francis
<alistair.fran...@xilinx.com> wrote:
> Originally the endi PVR bits were manually set for each machine. This
> is a hassle and difficult to read, instead set them based on the CPU
> properties.
>
> Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com>
> Reviewed-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
> ---
> hw/microblaze/petalogix_ml605_mmu.c | 2 +-
> target-microblaze/cpu-qom.h | 1 +
> target-microblaze/cpu.c | 2 ++
> target-microblaze/cpu.h | 2 +-
> 4 files changed, 5 insertions(+), 2 deletions(-)
>
> diff --git a/hw/microblaze/petalogix_ml605_mmu.c
> b/hw/microblaze/petalogix_ml605_mmu.c
> index 995a579..e9adc2f 100644
> --- a/hw/microblaze/petalogix_ml605_mmu.c
> +++ b/hw/microblaze/petalogix_ml605_mmu.c
> @@ -70,7 +70,6 @@ static void machine_cpu_reset(MicroBlazeCPU *cpu)
>
> env->pvr.regs[10] = 0x0e000000; /* virtex 6 */
> /* setup pvr to match kernel setting */
> - env->pvr.regs[0] |= PVR0_ENDI;
> env->pvr.regs[0] = (env->pvr.regs[0] & ~PVR0_VERSION_MASK) | (0x14 << 8);
> env->pvr.regs[4] = 0xc56b8000;
> env->pvr.regs[5] = 0xc56be000;
> @@ -99,6 +98,7 @@ petalogix_ml605_init(MachineState *machine)
> object_property_set_int(OBJECT(cpu), 1, "use-fpu", &error_abort);
> object_property_set_bool(OBJECT(cpu), true, "dcache-writeback",
> &error_abort);
> + object_property_set_bool(OBJECT(cpu), true, "endianness", &error_abort);
> object_property_set_bool(OBJECT(cpu), true, "realized", &error_abort);
>
> /* Attach emulated BRAM through the LMB. */
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index 3b6165d..d1d814b 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -66,6 +66,7 @@ typedef struct MicroBlazeCPU {
> uint8_t use_fpu;
> bool use_mmu;
> bool dcache_writeback;
> + bool endi;
> } cfg;
>
> CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 92c51a0..e6167d5 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -115,6 +115,7 @@ static void mb_cpu_realizefn(DeviceState *dev, Error
> **errp)
> env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
> (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0) |
> (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0);
> + (cpu->cfg.endi ? PVR0_ENDI_MASK : 0);
>
> env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
> (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
> @@ -174,6 +175,7 @@ static Property mb_properties[] = {
> DEFINE_PROP_BOOL("use-mmu", MicroBlazeCPU, cfg.use_mmu, true),
> DEFINE_PROP_BOOL("dcache-writeback", MicroBlazeCPU, cfg.dcache_writeback,
> false),
> + DEFINE_PROP_BOOL("endianness", MicroBlazeCPU, cfg.endi, false),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h
> index 54e41e8..0f82abd 100644
> --- a/target-microblaze/cpu.h
> +++ b/target-microblaze/cpu.h
> @@ -124,7 +124,7 @@ typedef struct CPUMBState CPUMBState;
> #define PVR0_USE_DCACHE_MASK 0x01000000
> #define PVR0_USE_MMU_MASK 0x00800000
> #define PVR0_USE_BTC 0x00400000
> -#define PVR0_ENDI 0x00200000
> +#define PVR0_ENDI_MASK 0x00200000
> #define PVR0_FAULT 0x00100000
> #define PVR0_VERSION_MASK 0x0000FF00
> #define PVR0_USER1_MASK 0x000000FF
> --
> 1.7.1
>
>
