On Thu, Jun 4, 2015 at 11:39 PM, Alistair Francis
<alistair.fran...@xilinx.com> wrote:
> Rename the usefpu variable to use_fpu.
>
> Signed-off-by: Alistair Francis <alistair.fran...@xilinx.com>
Reviewed-by: Peter Crosthwaite <peter.crosthwa...@xilinx.com>
> ---
> target-microblaze/cpu-qom.h | 2 +-
> target-microblaze/cpu.c | 8 ++++----
> target-microblaze/translate.c | 6 +++---
> 3 files changed, 8 insertions(+), 8 deletions(-)
>
> diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h
> index a6474f9..aa9c032 100644
> --- a/target-microblaze/cpu-qom.h
> +++ b/target-microblaze/cpu-qom.h
> @@ -63,7 +63,7 @@ typedef struct MicroBlazeCPU {
> struct {
> bool stackprot;
> uint32_t base_vectors;
> - uint8_t usefpu;
> + uint8_t use_fpu;
> } cfg;
>
> CPUMBState env;
> diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c
> index 13ae49a..a6b6fd7 100644
> --- a/target-microblaze/cpu.c
> +++ b/target-microblaze/cpu.c
> @@ -114,10 +114,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error
> **errp)
> | 0;
>
> env->pvr.regs[0] |= (cpu->cfg.stackprot ? PVR0_SPROT_MASK : 0) |
> - (cpu->cfg.usefpu ? PVR0_USE_FPU_MASK : 0);
> + (cpu->cfg.use_fpu ? PVR0_USE_FPU_MASK : 0);
>
> - env->pvr.regs[2] |= (cpu->cfg.usefpu ? PVR2_USE_FPU_MASK : 0) |
> - (cpu->cfg.usefpu > 1 ? PVR2_USE_FPU2_MASK : 0);
> + env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) |
> + (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0);
>
> env->pvr.regs[10] = 0x0c000000; /* Default to spartan 3a dsp family. */
> env->pvr.regs[11] = PVR11_USE_MMU | (16 << 17);
> @@ -167,7 +167,7 @@ static Property mb_properties[] = {
> * If use-fpu = 2 - Floating point conversion and square root
> instructions
> * are enabled
> */
> - DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.usefpu, 2),
> + DEFINE_PROP_UINT8("use-fpu", MicroBlazeCPU, cfg.use_fpu, 2),
> DEFINE_PROP_END_OF_LIST(),
> };
>
> diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c
> index 8187700..1f5fe9a 100644
> --- a/target-microblaze/translate.c
> +++ b/target-microblaze/translate.c
> @@ -1411,11 +1411,11 @@ static void dec_rts(DisasContext *dc)
>
> static int dec_check_fpuv2(DisasContext *dc)
> {
> - if ((dc->cpu->cfg.usefpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
> + if ((dc->cpu->cfg.use_fpu != 2) && (dc->tb_flags & MSR_EE_FLAG)) {
> tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_FPU);
> t_gen_raise_exception(dc, EXCP_HW_EXCP);
> }
> - return (dc->cpu->cfg.usefpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
> + return (dc->cpu->cfg.use_fpu == 2) ? 0 : PVR2_USE_FPU2_MASK;
> }
>
> static void dec_fpu(DisasContext *dc)
> @@ -1424,7 +1424,7 @@ static void dec_fpu(DisasContext *dc)
>
> if ((dc->tb_flags & MSR_EE_FLAG)
> && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)
> - && (dc->cpu->cfg.usefpu != 1)) {
> + && (dc->cpu->cfg.use_fpu != 1)) {
> tcg_gen_movi_tl(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP);
> t_gen_raise_exception(dc, EXCP_HW_EXCP);
> return;
> --
> 1.7.1
>
>
