On 04/22/15 10:09, Gerd Hoffmann wrote: > Hi, > >> tseg is just normal ram (yes, located at the end of memory), but (once >> tseg is enabled) only cpus in smm mode are allowed to access it. >> Likewise busmaster dma access is rejected, so non-smm code can't use the >> sata controller to access this indirectly. > > Update: Seems tseg can be anywhere, there is a "tseg memory base" > register @ 0xac in pci config space. > > Placing it at the end of memory is just what the bios is supposed to do > by default. And it makes sense to place it there. > > <quote> > This register contains the base address of TSEG DRAM memory. BIOS > determines the base of TSEG memory by subtracting the TSEG size (PCI > Device 0, offset 9Eh, bits 2:1) from graphics GTT stolen base (PCI > Device 0, offset A8h, bits 31:20). > > Once D_LCK has been set, these bits becomes read only. > </quote> > > "GTT stolen base" equals "top of below-4g memory" for us because we > emulate the chipset variant without graphics in qemu.
Thanks, that sounds good. So, as far as I understand, no changes to what we've discussed thus far. But, I have another question -- am I allowed to use "top of below-4g memory" directly, as discussed earlier, or should I use the above PCI registers? The tseg size will actually come from me (because I'll select it), but the top I could take from "top of below-4g memory" (preferably, see earlier), or reading the 0xA8 register. Unless, of course 0xA8 won't be implemented at all, *because* "we emulate the chipset variant without graphics in qemu." In other words, if the 0xA8 register is dependent on the integrated graphics, then I don't have a question. :) Thanks! Laszlo