Hi, > tseg is just normal ram (yes, located at the end of memory), but (once > tseg is enabled) only cpus in smm mode are allowed to access it. > Likewise busmaster dma access is rejected, so non-smm code can't use the > sata controller to access this indirectly.
Update: Seems tseg can be anywhere, there is a "tseg memory base" register @ 0xac in pci config space. Placing it at the end of memory is just what the bios is supposed to do by default. And it makes sense to place it there. <quote> This register contains the base address of TSEG DRAM memory. BIOS determines the base of TSEG memory by subtracting the TSEG size (PCI Device 0, offset 9Eh, bits 2:1) from graphics GTT stolen base (PCI Device 0, offset A8h, bits 31:20). Once D_LCK has been set, these bits becomes read only. </quote> "GTT stolen base" equals "top of below-4g memory" for us because we emulate the chipset variant without graphics in qemu. cheers, Gerd
