Hi Peter and all, Xilinx's next gen SoC has been announced. This series adds a SoC and machine model.
Series start with addition of ARM cortex A53 support (P1 and P2). The Soc skeleton is then added with GIC, EMACs and UARTs are added. The pre-existing models for GEM and UART are not SoC friendly (no visible state struct), so those are refactored for SoC. Create a generic machine model that exposes just the RAW SoC itself. The only external device modelled is DDR RAM, as driven by the -m option. The standard bootloader and PSCI support is used. Regards, Peter Peter Crosthwaite (15): target-arm: cpu64: Factor out ARM cortex init target-arm: cpu64: Add support for cortex-a53 arm: Introduce Xilinx Zynq MPSoC arm: xlnx-zynq-mp: Add GIC arm: xlnx-zynq-mp: Connect CPU Timers to GIC net: cadence_gem: Clean up variable names net: cadence_gem: Split state struct and type into header arm: xilinx-zynq-mp: Add GEM support char: cadence_uart: Clean up variable names char: cadence_uart: Split state struct and type into header arm: xilinx-zynq-mp: Add UART support arm: Add xilinx-zynq-mp-generic machine arm: xilinx-zynq-mp-generic: Add external RAM arm: xilinx-zynq-mp-generic: Add bootloading arm: xlnx-zynq-mp: Add PSCI setup default-configs/aarch64-softmmu.mak | 2 +- hw/arm/Makefile.objs | 1 + hw/arm/xlnx-zynq-mp-generic.c | 67 +++++++++++++++ hw/arm/xlnx-zynq-mp.c | 167 ++++++++++++++++++++++++++++++++++++ hw/char/cadence_uart.c | 113 ++++++++++-------------- hw/net/cadence_gem.c | 95 ++++++-------------- include/hw/arm/xlnx-zynq-mp.h | 29 +++++++ include/hw/char/cadence_uart.h | 35 ++++++++ include/hw/net/cadence_gem.h | 49 +++++++++++ target-arm/cpu64.c | 47 +++++++--- 10 files changed, 456 insertions(+), 149 deletions(-) create mode 100644 hw/arm/xlnx-zynq-mp-generic.c create mode 100644 hw/arm/xlnx-zynq-mp.c create mode 100644 include/hw/arm/xlnx-zynq-mp.h create mode 100644 include/hw/char/cadence_uart.h create mode 100644 include/hw/net/cadence_gem.h -- 2.3.0.1.g27a12f1
