Version 10 of the ARM processor security extension (TrustZone) support. This patchset includes changes to support the processor security extensions on ARMv7 aarch32 with hooks for later enabling v8 aarch64/32.
This is a rebase of v9 to a more recent master as well as a fix for an overlooked bug in patch 12 that broke AA64. Fabian Aggeler (19): target-arm: add banked register accessors target-arm: add CPREG secure state support target-arm: insert AArch32 cpregs twice into hashtable target-arm: move AArch32 SCR into security reglist target-arm: implement IRQ/FIQ routing to Monitor mode target-arm: add NSACR register target-arm: add MVBAR support target-arm: add SCTLR_EL3 and make SCTLR banked target-arm: respect SCR.FW, SCR.AW and SCTLR.NMFI target-arm: make CSSELR banked target-arm: make TTBR0/1 banked target-arm: make TTBCR banked target-arm: make DACR banked target-arm: make IFSR banked target-arm: make DFSR banked target-arm: make IFAR/DFAR banked target-arm: make PAR banked target-arm: make c13 cp regs banked (FCSEIDR, ...) target-arm: add cpu feature EL3 to CPUs with Security Extensions Greg Bellows (6): target-arm: extend async excp masking target-arm: add async excp target_el function target-arm: add secure state bit to CPREG hash target-arm: add SDER definition target-arm: make VBAR banked target-arm: make MAIR0/1 banked Sergey Fedorov (1): target-arm: add non-secure Translation Block flag hw/arm/pxa2xx.c | 6 +- linux-user/aarch64/target_cpu.h | 2 +- linux-user/arm/target_cpu.h | 2 +- linux-user/main.c | 2 +- target-arm/cpu.c | 14 +- target-arm/cpu.h | 364 ++++++++++++++++++--- target-arm/helper.c | 682 ++++++++++++++++++++++++++++++---------- target-arm/internals.h | 6 +- target-arm/op_helper.c | 4 +- target-arm/translate.c | 15 +- target-arm/translate.h | 1 + 11 files changed, 868 insertions(+), 230 deletions(-) -- 1.8.3.2
