On 31 October 2014 11:24, Peter Maydell <peter.mayd...@linaro.org> wrote:
> On 30 October 2014 21:28, Greg Bellows <greg.bell...@linaro.org> wrote:
> > From: Fabian Aggeler <aggel...@ethz.ch>
> >
> > When EL3 is running in AArch32 (or ARMv7 with Security Extensions)
> > IFAR and DFAR have a secure and a non-secure instance.
> >
> > Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
> > Signed-off-by: Greg Bellows <greg.bell...@linaro.org>
> >
> > ---
> >
> > v3 -> v4
> > - Revert to array-based notation of far_el in combination with v7 naming
> > ---
> > target-arm/cpu.c | 2 +-
> > target-arm/cpu.h | 19 ++++++++++++++++++-
> > target-arm/helper.c | 20 +++++++++++---------
> > 3 files changed, 30 insertions(+), 11 deletions(-)
> >
> > diff --git a/target-arm/cpu.c b/target-arm/cpu.c
> > index 18f4726..a711834 100644
> > --- a/target-arm/cpu.c
> > +++ b/target-arm/cpu.c
> > @@ -522,7 +522,7 @@ static void arm1026_initfn(Object *obj)
> > ARMCPRegInfo ifar = {
> > .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0,
> .opc2 = 1,
> > .access = PL1_RW,
> > - .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
> > + .fieldoffset = offsetof(CPUARMState, cp15.ifar_ns),
> > .resetvalue = 0
> > };
> > define_one_arm_cp_reg(cpu, &ifar);
> > diff --git a/target-arm/cpu.h b/target-arm/cpu.h
> > index 29bf273..10985d4 100644
> > --- a/target-arm/cpu.h
> > +++ b/target-arm/cpu.h
> > @@ -270,7 +270,24 @@ typedef struct CPUARMState {
> > uint64_t esr_el[4];
> > };
> > uint32_t c6_region[8]; /* MPU base/size registers. */
> > - uint64_t far_el[4]; /* Fault address registers. */
> > + union { /* Fault address registers. */
> > + struct {
> > + uint64_t _unused_far0;
> > +#ifdef HOST_WORDS_BIGENDIAN
> > + uint32_t ifar_ns;
> > + uint32_t dfar_ns;
> > + uint32_t ifar_s;
> > + uint32_t dfar_s;
> > +#else
> > + uint32_t dfar_ns;
> > + uint32_t ifar_ns;
> > + uint32_t dfar_s;
> > + uint32_t ifar_s;
> > +#endif
>
> This is pretty ugly but I guess I can live with it.
>
> > + uint64_t _unused_far3;;
>
> Stray extra semicolon.
>
>
Fixed in v9.
> > + };
> > + uint64_t far_el[4];
> > + };
> > uint64_t par_el1; /* Translation result. */
> > uint32_t c9_insn; /* Cache lockdown registers. */
> > uint32_t c9_data;
> > diff --git a/target-arm/helper.c b/target-arm/helper.c
> > index c5948f7..c4d0db4 100644
> > --- a/target-arm/helper.c
> > +++ b/target-arm/helper.c
> > @@ -554,7 +554,8 @@ static const ARMCPRegInfo v6_cp_reginfo[] = {
> > .access = PL0_W, .type = ARM_CP_NOP },
> > { .name = "IFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 =
> 2,
> > .access = PL1_RW,
> > - .fieldoffset = offsetofhigh32(CPUARMState, cp15.far_el[1]),
> > + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.ifar_s),
> > + offsetof(CPUARMState, cp15.ifar_ns) },
> > .resetvalue = 0, },
> > /* Watchpoint Fault Address Register : should actually only be
> present
> > * for 1136, 1176, 11MPCore.
> > @@ -1681,11 +1682,14 @@ static const ARMCPRegInfo vmsa_cp_reginfo[] = {
> > .resetfn = arm_cp_reset_ignore, .raw_writefn =
> vmsa_ttbcr_raw_write,
> > .bank_fieldoffsets = { offsetoflow32(CPUARMState, cp15.ttbcr_s),
> > offsetoflow32(CPUARMState, cp15.ttbcr_ns)
> } },
> > - /* 64-bit FAR; this entry also gives us the AArch32 DFAR */
> > - { .name = "FAR_EL1", .state = ARM_CP_STATE_BOTH,
> > + { .name = "DFAR", .cp = 15, .crn = 6, .crm = 0, .opc1 = 0, .opc2 =
> 0,
> > + .access = PL1_RW, .resetvalue = 0,
> > + .bank_fieldoffsets = { offsetof(CPUARMState, cp15.dfar_s),
> > + offsetof(CPUARMState, cp15.dfar_ns) } },
> > + { .name = "FAR_EL1", .state = ARM_CP_STATE_AA64,
> > .opc0 = 3, .crn = 6, .crm = 0, .opc1 = 0, .opc2 = 0,
> > - .access = PL1_RW, .fieldoffset = offsetof(CPUARMState,
> cp15.far_el[1]),
> > - .resetvalue = 0, },
> > + .access = PL1_RW, .resetvalue = 0,
> > + .fieldoffset = offsetof(CPUARMState, cp15.far_el[1]) },
>
> This change just seems to be rearranging the fields for no particular
> reason?
>
Will fix in v9.
>
> > REGINFO_SENTINEL
> > };
> >
> > @@ -4300,8 +4304,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
> > /* Fall through to prefetch abort. */
> > case EXCP_PREFETCH_ABORT:
> > A32_BANKED_CURRENT_REG_SET(env, ifsr, env->exception.fsr);
> > - env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 32, 32,
> > - env->exception.vaddress);
> > + A32_BANKED_CURRENT_REG_SET(env, ifar, env->exception.vaddress);
> > qemu_log_mask(CPU_LOG_INT, "...with IFSR 0x%x IFAR 0x%x\n",
> > env->exception.fsr,
> (uint32_t)env->exception.vaddress);
> > new_mode = ARM_CPU_MODE_ABT;
> > @@ -4311,8 +4314,7 @@ void arm_cpu_do_interrupt(CPUState *cs)
> > break;
> > case EXCP_DATA_ABORT:
> > A32_BANKED_CURRENT_REG_SET(env, dfsr, env->exception.fsr);
> > - env->cp15.far_el[1] = deposit64(env->cp15.far_el[1], 0, 32,
> > - env->exception.vaddress);
> > + A32_BANKED_CURRENT_REG_SET(env, dfar, env->exception.vaddress);
> > qemu_log_mask(CPU_LOG_INT, "...with DFSR 0x%x DFAR 0x%x\n",
> > env->exception.fsr,
> > (uint32_t)env->exception.vaddress);
>
> Otherwise has my reviewed-by.
>
> -- PMM
>
