On 10/01/2014 02:35 AM, Bastian Koppelmann wrote: > + case OPC2_32_BO_ST_A_PREINC: > + tcg_gen_addi_tl(cpu_gpr_a[r2], cpu_gpr_a[r2], off10); > + tcg_gen_qemu_st_tl(cpu_gpr_a[r1], cpu_gpr_a[r2], ctx->mem_idx, > + MO_LESL); > + break;
The writeback to A[r2] should not happen until after the memory operation, so that if a memory exception occurs, A[r2] is not adjusted. r~
