On Sun, Aug 03, 2014 at 10:53:45AM +0200, Adam Lackorzynski wrote:
> The GICD_ICFGR register covers 4 interrupts per byte.
>
> Signed-off-by: Adam Lackorzynski <a...@os.inf.tu-dresden.de>
> ---
> hw/intc/arm_gic.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c
> index 1532ef9..d2b1aaf 100644
> --- a/hw/intc/arm_gic.c
> +++ b/hw/intc/arm_gic.c
> @@ -372,7 +372,7 @@ static uint32_t gic_dist_readb(void *opaque, hwaddr
> offset)
> }
> } else if (offset < 0xf00) {
> /* Interrupt Configuration. */
> - irq = (offset - 0xc00) * 2 + GIC_BASE_IRQ;
> + irq = (offset - 0xc00) * 4 + GIC_BASE_IRQ;
> if (irq >= s->num_irq)
> goto bad_reg;
> res = 0;
> --
> 2.0.1
>
>
I guess we should consider only getting/setting the LSB of each field if
we're emulating a GICv1, but:
Acked-by: Christoffer Dall <christoffer.d...@linaro.org>
