Each individual architecture needs to use the qemu_log_in_addr_range() feature for enabling in_asm and marking blocks for op/opt_op output.
Signed-off-by: Alex Bennée <alex.ben...@linaro.org> diff --git a/target-arm/translate-a64.c b/target-arm/translate-a64.c index 33b5025..56b8534 100644 --- a/target-arm/translate-a64.c +++ b/target-arm/translate-a64.c @@ -10910,7 +10910,8 @@ void gen_intermediate_code_internal_a64(ARMCPU *cpu, gen_io_start(); } - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT) && + qemu_log_in_addr_range(dc->pc))) { tcg_gen_debug_insn_start(dc->pc); } @@ -10984,7 +10985,8 @@ done_generating: *tcg_ctx.gen_opc_ptr = INDEX_op_end; #ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && + qemu_log_in_addr_range(pc_start)) { qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); log_target_disas(env, pc_start, dc->pc - pc_start, diff --git a/target-arm/translate.c b/target-arm/translate.c index cf4e767..d74a8a9 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -11018,7 +11018,8 @@ static inline void gen_intermediate_code_internal(ARMCPU *cpu, if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); - if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { + if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT)) && + qemu_log_in_addr_range(dc->pc)) { tcg_gen_debug_insn_start(dc->pc); } @@ -11138,7 +11139,8 @@ done_generating: *tcg_ctx.gen_opc_ptr = INDEX_op_end; #ifdef DEBUG_DISAS - if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM)) { + if (qemu_loglevel_mask(CPU_LOG_TB_IN_ASM) && + qemu_log_in_addr_range(pc_start)) { qemu_log("----------------\n"); qemu_log("IN: %s\n", lookup_symbol(pc_start)); log_target_disas(env, pc_start, dc->pc - pc_start, -- 2.0.3