From: Greg Bellows <greg.bell...@linaro.org>
Updated Fabian's v3 patchset for review comments. This patchset includes
changes in support of the security extension on v7 aarch32 with hooks for later
enabling v8 aarch64.
The patches are built upon and therefore dependent on v3 of Xilinx's second
round of EL2/3 patches.
Summary of the changes from v3 -> v4:
* Conditionally register security CP registers.
* Fixed various bugs found in review
* Reverted back to EL array-notation in combination with explicit v7 naming
* Add functionality to handle migration of duplicate CP registrations
Fabian Aggeler (29):
target-arm: add cpu feature EL3 to CPUs with Security Extensions
target-arm: move Aarch32 SCR into security reglist
target-arm: increase arrays of registers R13 & R14
target-arm: add arm_is_secure() function
target-arm: make arm_current_pl() return PL3
target-arm: A32: Emulate the SMC instruction
target-arm: extend Aarch32 async excp masking
target-arm: extend Aarch64 SCR.{FIQ|IRQ} handling
target-arm: add async excp target_el&mode function
target-arm: use dedicated target_el function
target-arm: implement IRQ/FIQ routing to Monitor mode
target-arm: Respect SCR.FW, SCR.AW and SCTLR.NMFI
target-arm: add NSACR register
target-arm: add MVBAR support
target-arm: add macros to access banked registers
target-arm: insert Aarch32 cpregs twice into hashtable
target-arm: arrayfying fieldoffset for banking
target-arm: add SCTLR_EL3 and make SCTLR banked
target-arm: make CSSELR banked
target-arm: add TTBR0_EL3 and make TTBR0/1 banked
target-arm: add TCR_EL3 and make TTBCR banked
target-arm: make c2_mask and c2_base_mask banked
target-arm: make DACR banked
target-arm: make IFSR banked
target-arm: make DFSR banked
target-arm: make IFAR/DFAR banked
target-arm: make PAR banked
target-arm: make VBAR banked
target-arm: make c13 cp regs banked (FCSEIDR, ...)
Greg Bellows (1):
target-arm: Limit migration of duplicate CP regs
Sergey Fedorov (3):
target-arm: reject switching to monitor mode
target-arm: add non-secure Translation Block flag
target-arm: add SDER definition
hw/arm/pxa2xx.c | 4 +-
target-arm/cpu.c | 11 +-
target-arm/cpu.h | 446 +++++++++++++++++++++++++---
target-arm/helper.c | 722 +++++++++++++++++++++++++++++++++++----------
target-arm/internals.h | 5 +
target-arm/machine.c | 4 +-
target-arm/op_helper.c | 2 +-
target-arm/translate-a64.c | 1 +
target-arm/translate.c | 57 +++-
target-arm/translate.h | 1 +
10 files changed, 1019 insertions(+), 234 deletions(-)
--
1.8.3.2
