On 21 May 2014, at 18:12, Peter Maydell <peter.mayd...@linaro.org> wrote:
> On 14 May 2014 06:43, Sergey Fedorov <serge.f...@gmail.com> wrote:
>>
>> On 13.05.2014 20:15, Fabian Aggeler wrote:
>>> From: Svetlana Fedoseeva <s.fedose...@samsung.com>
>>>
>>> Signed-off-by: Svetlana Fedoseeva <s.fedose...@samsung.com>
>>> Signed-off-by: Sergey Fedorov <s.fedo...@samsung.com>
>>> Signed-off-by: Fabian Aggeler <aggel...@ethz.ch>
>>> ---
>>> target-arm/helper.c | 5 +++++
>>> 1 file changed, 5 insertions(+)
>>>
>>> diff --git a/target-arm/helper.c b/target-arm/helper.c
>>> index 9c3269f..2b57ad9 100644
>>> --- a/target-arm/helper.c
>>> +++ b/target-arm/helper.c
>>> @@ -2083,6 +2083,11 @@ static void sctlr_write(CPUARMState *env, const
>>> ARMCPRegInfo *ri,
>>> {
>>> ARMCPU *cpu = arm_env_get_cpu(env);
>>>
>>> + if (arm_feature(env, ARM_FEATURE_V7)) {
>>> + value |= SCTLR_XP | SCTLR_U | SCTLR_nTWE | SCTLR_nTWI | SCTLR_L
>>> + | SCTLR_CP15BEN | SCTLR_P; /* These bits are RAO/WI */
>>
>> Actually, some of these bits are RAO/WI since v6. Also, there are some
>> RAZ/WI bits varying over architecture variants. There is some overview
>> at ARM ARM v7-AP section L.7.4. Maybe it is worth to fix more precisely
>> over supported architecture variants? By the way, this patch could be
>> separated from security extensions support patch set.
>
> Agreed. Our compliance for bits that should-be-0/1 is not great,
> but if we don't actually need to do those fixes for TZ support
> then they're probably better separated out (ie drop them from
> this patchset for the moment and submit them separately or
> later...)
>
> Also for v8 many of these RAZ/RAO bits become RES0/RES1 and
> the rules are different...
>
> thanks
> — PMM
Okay, I will separate them and submit them separately.
Thanks,
Fabian
