From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com> Hi,
I've been doing some work on modeling parts of EL2 and 3 + some of the system-wide virtualization features for ARMv8. A lot is missing but I've got a series with enough to for example run KVM A64 guests on top of EL3 firmware inside emulated QEMU A64 VMs. I'm working on cleaning things up and plan to send patches and publish things as I go. This series does a first round of preparations. Most of it has little or no user visible impact as the EL2 and 3 features remain disabled. For the arrayification of the various EL regs that do not exist for EL0, I've now switched to using padded arrays with the index beeing the EL nr. Regarding the discussion on 1:1 mapping between EL and MMU-idx: http://lists.gnu.org/archive/html/qemu-devel/2014-05/msg03563.html I've appended two RFC patches and the end of the series showing what a switch to 1:1 mapping between EL and MMU-idx could look like. If the 1:1 mapping is prefered, I'll fold the patches for the next spin. Happy to address any comments people may have. Cheers, Edgar v2 -> v3: * Rephrase comment in update_spsel * Switch arrayification pattern to padded with el as index. * Rename arm64_spsr_banked_index to aarch64_spsr_banked_index. * Avoid using the result from aarch64_spsr_banked_index in a32 mode. * aarch64 - > AArch64 in comments. * Make VBAR_EL2 RES0 if EL2 is not enabled but higher ELs are. * Drop friendly DAIF logging * Squash Add storage for VBAR_EL2 and 3 into reg of VBAR v1 -> v2: * Name hyp and mon in cpu_mode_names[] * Friendly log of full DAIF, delimited by space * Use raw_write in vbar_write * Blank line after MMU IDX * Use 1:1 EL array mapping in arm64_banked_spsr_index * Fix typo in commit message adding arm64_banked_spsr_index. * Register EL2 and EL3 regs outside if ARM_FEATURE_V8 * Avoid split declaration in exception_return * Merge comments in exception_return * Use VBAR_EL_IDX when registering VBAR_EL2 and 3. Edgar E. Iglesias (22): target-arm: Make elr_el1 an array target-arm: Make esr_el1 an array target-arm: c12_vbar -> vbar_el[] target-arm: Add arm_el_to_mmu_idx() target-arm: Move get_mem_index to translate.h target-arm: A64: Add SP entries for EL2 and 3 target-arm: A64: Add ELR entries for EL2 and 3 target-arm: Add SPSR entries for EL2/HYP and EL3/MON target-arm: A64: Introduce aarch64_banked_spsr_index() target-arm: Add a feature flag for EL2 target-arm: Add a feature flag for EL3 target-arm: Register EL2 versions of ELR and SPSR target-arm: Register EL3 versions of ELR and SPSR target-arm: A64: Forbid ERET to increase the EL target-arm: A64: Forbid ERET to unimplemented ELs target-arm: A64: Generalize ERET to various ELs target-arm: A64: Generalize update_spsel for the various ELs target-arm: Make vbar_write writeback to any CPREG target-arm: A64: Register VBAR_EL2 target-arm: A64: Register VBAR_EL3 RFC: target-arm: A32: Use get_mem_index for load/stores RFC: target-arm: Use a 1:1 mapping between EL and MMU index target-arm/cpu.h | 24 +++-- target-arm/helper-a64.c | 12 +-- target-arm/helper.c | 80 ++++++++++++++-- target-arm/internals.h | 25 ++++- target-arm/kvm64.c | 4 +- target-arm/machine.c | 10 +- target-arm/op_helper.c | 19 ++-- target-arm/translate-a64.c | 9 -- target-arm/translate.c | 224 +++++++++++++++++++++++---------------------- target-arm/translate.h | 5 + 10 files changed, 251 insertions(+), 161 deletions(-) -- 1.8.3.2
