Il 13/05/2014 20:57, Paolo Bonzini ha scritto:
Il 13/05/2014 20:39, Kevin O'Connor ha scritto:
That doesn't sound right. What happens if the processor takes an NMI,
SMI, or VMEXIT between the point it enables protected mode but before
it long jumps? The processor would have to save and restore the CPL
somewhere for all of these situations.
For VMEXITs it's up to the hypervisor to make it work properly. I just
posted today fixes for KVM.
I guess the answer for NMIs is "good luck". But in the case of NMIs,
wouldn't it be broken anyway, because the IDT format is different
between real mode and protected mode?
For SMIs, http://www.sandpile.org/x86/smm.htm says that the CPL is
stored somewhere in SMRAM. I think your patches are an improvement
anyway, we can build a more complete fix on top of them.
On second thought, the CPL should always be equal to SS.DPL, even during
real mode transitions. Unlike CS.RPL, SS.DPL is hidden in the internal
segment descriptor registers and is always zero.
I say *should*, because of course there is an exception. :) CPL is
forced to 3 by SYSRET, even if it loads SS with a selector whose RPL is
not 3. So we're better off saving CPL in SMRAM (and perhaps make the
SMRAM map equal to that of real processors).
In any case, I think this is an example of how your patches are an
improvement; it would be trivial to make CPL=SS.DPL on top of them.
Paolo
