Am 02.05.2014 16:33, schrieb Paolo Bonzini: > The PIIX datasheet says that "before another INIT pulse can be > generated via [port 92h], [bit 0] must be written back to a > zero. > > This bug is masked right now because a full reset will clear the > value of port 92h. But once we implement soft reset correctly, > the next attempt to enable the A20 line by setting bit 1 (and > leaving the others untouched) will cause another reset. > > Reviewed-by: Anthony Liguori <aligu...@us.ibm.com> > Signed-off-by: Paolo Bonzini <pbonz...@redhat.com>
Reviewed-by: Andreas Färber <afaer...@suse.de> Andreas -- SUSE LINUX Products GmbH, Maxfeldstr. 5, 90409 Nürnberg, Germany GF: Jeff Hawn, Jennifer Guild, Felix Imendörffer; HRB 16746 AG Nürnberg
