Edgar E. Iglesias <edgar.igles...@gmail.com> writes:
> From: "Edgar E. Iglesias" <edgar.igles...@xilinx.com>
>
> Harmless typo as opc1 defaults to zero and opc2 gets
> re-declared to its correct value.
>
> Signed-off-by: Edgar E. Iglesias <edgar.igles...@xilinx.com>
Reviewed-by: Alex Bennée <alex.ben...@linaro.org>
> ---
> target-arm/helper.c | 24 ++++++++++++------------
> 1 file changed, 12 insertions(+), 12 deletions(-)
>
> diff --git a/target-arm/helper.c b/target-arm/helper.c
> index 330bfc7..0b8e8aa 100644
> --- a/target-arm/helper.c
> +++ b/target-arm/helper.c
> @@ -1893,51 +1893,51 @@ static const ARMCPRegInfo v8_cp_reginfo[] = {
> .access = PL1_W, .type = ARM_CP_NOP },
> /* TLBI operations */
> { .name = "TLBI_VMALLE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 0,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 0,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbiall_write },
> { .name = "TLBI_VAE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 1,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 1,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_va_write },
> { .name = "TLBI_ASIDE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 2,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 2,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_asid_write },
> { .name = "TLBI_VAAE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 3,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 3,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_vaa_write },
> { .name = "TLBI_VALE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 5,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 5,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_va_write },
> { .name = "TLBI_VAALE1IS", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 3, .opc2 = 7,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 3, .opc2 = 7,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_vaa_write },
> { .name = "TLBI_VMALLE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 0,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 0,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbiall_write },
> { .name = "TLBI_VAE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 1,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 1,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_va_write },
> { .name = "TLBI_ASIDE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 2,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 2,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_asid_write },
> { .name = "TLBI_VAAE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 3,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 3,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_vaa_write },
> { .name = "TLBI_VALE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 5,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 5,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_va_write },
> { .name = "TLBI_VAALE1", .state = ARM_CP_STATE_AA64,
> - .opc0 = 1, .opc2 = 0, .crn = 8, .crm = 7, .opc2 = 7,
> + .opc0 = 1, .opc1 = 0, .crn = 8, .crm = 7, .opc2 = 7,
> .access = PL1_W, .type = ARM_CP_NO_MIGRATE,
> .writefn = tlbi_aa64_vaa_write },
> #ifndef CONFIG_USER_ONLY
--
Alex Bennée
