This patch series addresses bugs in the recently added VSX instructions. Two
general
defects are fixed:
(1) The VSX Convert to Integer instructions truncate the source floating point
number to an integer value and hence should use a round-to-zero rounding
algorithm. The existing implementation erroneously uses the rounding
mode as set by the FPSCR.
This patch was previously published separately (see discussion at
http://lists.nongnu.org/archive/html/qemu-devel/2014-03/msg04526.html).
(2) There is a pervasive problem with the VSX helpers on Little Endian hosts.
The bug can be seen when using a mixture of VSRs in the upper and lower
regions of VSR (i.e. a mixture of VSR 0-31, which overlay the Floating
Point register array, and VSR 32-64 which overlay the Altivec AVR array).
This patch series introduces VSR field accessors that are consistent with
the Power ISA notation irrespective of host endianness. The VSX
instruction
macros are updated to use these accessors.
For example, the Power ISA has pictures like this, describing a VSR:
0 32 64 96 127
+----------+----------+----------+----------+
| .word[0] | .word[1] | .word[2] | .word[3] |
+----------+----------+----------+----------+
The updated code will now refer to .word[0] as v->VsrW(0), .word[1]
as v->VsrW(1), and so on.
This change makes the code correct and also more consistent with the ISA
document.
Tom Musta (9):
softfloat: Introduce float32_to_uint64_round_to_zero
target-ppc: Bug: VSX Convert to Integer Should Truncate
target-ppc: Define Endian-Correct Accessors for VSR Field Acess
target-ppc: Correct LE Host Inversion of Lower VSRs
target-ppc: Correct Simple VSR LE Host Inversions
target-ppc: Correct VSX Scalar Compares
target-ppc: Correct VSX FP to FP Conversions
target-ppc: Correct VSX FP to Integer Conversion
target-ppc: Correct VSX Integer to FP Conversion
fpu/softfloat.c | 54 +++++
include/fpu/softfloat.h | 1 +
target-ppc/fpu_helper.c | 494 +++++++++++++++++++++++------------------------
3 files changed, 298 insertions(+), 251 deletions(-)
