Signed-off-by: Richard Henderson <r...@twiddle.net>
---
tcg/aarch64/tcg-target.c | 67 +++++++++++++++++-------------------------------
1 file changed, 24 insertions(+), 43 deletions(-)
diff --git a/tcg/aarch64/tcg-target.c b/tcg/aarch64/tcg-target.c
index 0735ffe..f9d9703 100644
--- a/tcg/aarch64/tcg-target.c
+++ b/tcg/aarch64/tcg-target.c
@@ -1149,21 +1149,21 @@ static void tcg_out_qemu_st_direct(TCGContext *s,
TCGMemOp memop,
tcg_out_ldst_r(s, MO_8, LDST_ST, data_r, addr_r, off_r);
break;
case MO_16:
- if (bswap) {
+ if (bswap && data_r != TCG_REG_XZR) {
tcg_out_rev16(s, TCG_TYPE_I32, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, MO_16, LDST_ST, data_r, addr_r, off_r);
break;
case MO_32:
- if (bswap) {
+ if (bswap && data_r != TCG_REG_XZR) {
tcg_out_rev(s, TCG_TYPE_I32, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
tcg_out_ldst_r(s, MO_32, LDST_ST, data_r, addr_r, off_r);
break;
case MO_64:
- if (bswap) {
+ if (bswap && data_r != TCG_REG_XZR) {
tcg_out_rev(s, TCG_TYPE_I64, TCG_REG_TMP, data_r);
data_r = TCG_REG_TMP;
}
@@ -1174,22 +1174,13 @@ static void tcg_out_qemu_st_direct(TCGContext *s,
TCGMemOp memop,
}
}
-static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args)
+static void tcg_out_qemu_ld(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+ TCGMemOp memop, int mem_index)
{
- TCGReg addr_reg, data_reg;
- TCGMemOp memop;
#ifdef CONFIG_SOFTMMU
- int mem_index;
- TCGMemOp s_bits;
+ TCGMemOp s_bits = memop & MO_SIZE;
uint8_t *label_ptr;
-#endif
- data_reg = args[0];
- addr_reg = args[1];
- memop = args[2];
-#ifdef CONFIG_SOFTMMU
- mem_index = args[3];
- s_bits = memop & MO_SIZE;
tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 1);
tcg_out_qemu_ld_direct(s, memop, data_reg, addr_reg, TCG_REG_X1);
add_qemu_ldst_label(s, 1, memop, data_reg, addr_reg,
@@ -1200,22 +1191,12 @@ static void tcg_out_qemu_ld(TCGContext *s, const TCGArg
*args)
#endif /* CONFIG_SOFTMMU */
}
-static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args)
+static void tcg_out_qemu_st(TCGContext *s, TCGReg data_reg, TCGReg addr_reg,
+ TCGMemOp memop, int mem_index)
{
- TCGReg addr_reg, data_reg;
- TCGMemOp memop;
#ifdef CONFIG_SOFTMMU
- int mem_index;
- TCGMemOp s_bits;
+ TCGMemOp s_bits = memop & MO_SIZE;
uint8_t *label_ptr;
-#endif
- data_reg = args[0];
- addr_reg = args[1];
- memop = args[2];
-
-#ifdef CONFIG_SOFTMMU
- mem_index = args[3];
- s_bits = memop & MO_SIZE;
tcg_out_tlb_read(s, addr_reg, s_bits, &label_ptr, mem_index, 0);
tcg_out_qemu_st_direct(s, memop, data_reg, addr_reg, TCG_REG_X1);
@@ -1310,18 +1291,18 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_st8_i32:
case INDEX_op_st8_i64:
- tcg_out_ldst(s, MO_8, LDST_ST, a0, a1, a2);
+ tcg_out_ldst(s, MO_8, LDST_ST, REG0(0), a1, a2);
break;
case INDEX_op_st16_i32:
case INDEX_op_st16_i64:
- tcg_out_ldst(s, MO_16, LDST_ST, a0, a1, a2);
+ tcg_out_ldst(s, MO_16, LDST_ST, REG0(0), a1, a2);
break;
case INDEX_op_st_i32:
case INDEX_op_st32_i64:
- tcg_out_ldst(s, MO_32, LDST_ST, a0, a1, a2);
+ tcg_out_ldst(s, MO_32, LDST_ST, REG0(0), a1, a2);
break;
case INDEX_op_st_i64:
- tcg_out_ldst(s, MO_64, LDST_ST, a0, a1, a2);
+ tcg_out_ldst(s, MO_64, LDST_ST, REG0(0), a1, a2);
break;
case INDEX_op_add_i32:
@@ -1520,11 +1501,11 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc,
case INDEX_op_qemu_ld_i32:
case INDEX_op_qemu_ld_i64:
- tcg_out_qemu_ld(s, args);
+ tcg_out_qemu_ld(s, a0, a1, a2, args[3]);
break;
case INDEX_op_qemu_st_i32:
case INDEX_op_qemu_st_i64:
- tcg_out_qemu_st(s, args);
+ tcg_out_qemu_st(s, REG0(0), a1, a2, args[3]);
break;
case INDEX_op_bswap32_i64:
@@ -1632,13 +1613,13 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_ld32s_i64, { "r", "r" } },
{ INDEX_op_ld_i64, { "r", "r" } },
- { INDEX_op_st8_i32, { "r", "r" } },
- { INDEX_op_st16_i32, { "r", "r" } },
- { INDEX_op_st_i32, { "r", "r" } },
- { INDEX_op_st8_i64, { "r", "r" } },
- { INDEX_op_st16_i64, { "r", "r" } },
- { INDEX_op_st32_i64, { "r", "r" } },
- { INDEX_op_st_i64, { "r", "r" } },
+ { INDEX_op_st8_i32, { "rZ", "r" } },
+ { INDEX_op_st16_i32, { "rZ", "r" } },
+ { INDEX_op_st_i32, { "rZ", "r" } },
+ { INDEX_op_st8_i64, { "rZ", "r" } },
+ { INDEX_op_st16_i64, { "rZ", "r" } },
+ { INDEX_op_st32_i64, { "rZ", "r" } },
+ { INDEX_op_st_i64, { "rZ", "r" } },
{ INDEX_op_add_i32, { "r", "r", "rwA" } },
{ INDEX_op_add_i64, { "r", "r", "rA" } },
@@ -1692,8 +1673,8 @@ static const TCGTargetOpDef aarch64_op_defs[] = {
{ INDEX_op_qemu_ld_i32, { "r", "l" } },
{ INDEX_op_qemu_ld_i64, { "r", "l" } },
- { INDEX_op_qemu_st_i32, { "l", "l" } },
- { INDEX_op_qemu_st_i64, { "l", "l" } },
+ { INDEX_op_qemu_st_i32, { "lZ", "l" } },
+ { INDEX_op_qemu_st_i64, { "lZ", "l" } },
{ INDEX_op_bswap16_i32, { "r", "r" } },
{ INDEX_op_bswap32_i32, { "r", "r" } },
--
1.8.5.3
