This patch series is kind of in two parts. The first 8 patches
are the "Neon second set" that's already been pretty much reviewed;
I'm resending them just because there were a few minor nits that
came up in the last round which have been fixed:
* patch 6 added the missing SQDMULH/SQRDMULH unallocated/unimplemented
case in the SIMD 3-same initial decode
* patch 7 now uses the _i32 vector element accessors
* patch 8 fixed a few codestyle nits
(RTH: these all seemed trivial enough that I've left your
reviewed-by tags in place).
Patches 9..21 are new, and fill in a number of gaps that bring
us up to (and past) parity with the SuSE tree for coverage:
* more SIMD 3-same ops, including basically all the integer ones
* the "scalar pairwise" instruction group
* more SIMD scalar-3-same ops, including all the integer ones
* some (but not all) of the 2-reg misc and scalar 2-reg misc groups
(by the same rationale as with 3-same, we aim for "anything
implemented in the SuSE tree" plus enough to make it reasonably
likely we've got the general function structure correct)
thanks
-- PMM
Alex Bennée (2):
target-arm: A64: Add SIMD shift by immediate
target-arm: A64: Add 2-reg-misc REV* instructions
Peter Maydell (19):
target-arm: A64: Add SIMD three-different multiply accumulate insns
target-arm: A64: Add SIMD three-different ABDL instructions
target-arm: A64: Add SIMD scalar 3 same add, sub and compare ops
target-arm: A64: Add top level decode for SIMD 3-same group
target-arm: A64: Add logic ops from SIMD 3 same group
target-arm: A64: Add integer ops from SIMD 3-same group
target-arm: A64: Add simple SIMD 3-same floating point ops
target-arm: A64: Implement SIMD 3-reg-same shift and saturate insns
target-arm: A64: Implement remaining non-pairwise int SIMD 3-reg-same
insns
target-arm: A64: Implement pairwise integer ops from 3-reg-same SIMD
tcg: Add TCGV_UNUSED_PTR, TCGV_IS_UNUSED_PTR, TCGV_EQUAL_PTR
target-arm: A64: Implement scalar pairwise ops
target-arm: A64: Implement remaining integer scalar-3-same insns
target-arm: A64: Add SIMD simple 64 bit insns from scalar 2-reg misc
target-arm: A64: Add skeleton decode for SIMD 2-reg misc group
target-arm: A64: Implement 2-register misc compares, ABS, NEG
target-arm: A64: Implement 2-reg-misc CNT, NOT and RBIT
target-arm: A64: Add narrowing 2-reg-misc instructions
target-arm: A64: Add FNEG and FABS to the SIMD 2-reg-misc group
target-arm/helper.h | 1 +
target-arm/neon_helper.c | 12 +
target-arm/translate-a64.c | 2341 ++++++++++++++++++++++++++++++++++++++++++--
tcg/tcg.h | 3 +
4 files changed, 2299 insertions(+), 58 deletions(-)
--
1.8.5
