This is the fourth and final series of patches that add emulation support to QEMU for the PowerPC Vector Scalar Extension (VSX).
This series adds the instructions that were newly introduced with Power ISA V2.07. This includes 3 scalar load instructions, 2 scalar store instructions, 7 standard single precision scalar arithmetic instructions, 8 scalar single precision fused multiply/add instructions, two integer-to-single-precision conversion instructions and 3 vector logical instructions. The single-precision scalar arithmetic instructions all interpret the most significant 64 bits of a VSR as a single precision floating point number stored in double precision format (similar to the standard PowerPC floating point single precision instructions). Thus a common theme in the supporting code is rounding of an intermediate double-precision number to single precision. V2: (a) Changed the rounding to single precision to reuse the existing helper_frsp() routine. (b) Re-implemented the fused multiply/add instructions to use float32_muladd instead of float64_muladd, which avoids subtle rounding errors. V3: Re-implemented fused multiply/add per clarification from Richard Henderson. V4: Changed fused multiply/add to use helper_frsp (inadvertently re-injected when I used an earlier patch). V5: Fixed tcg compilation problems. V6: Added instructions that were previously missed. V7: Optimized m[ft]vsrd, fmrgow instructions. Changed signatures of some scalar helpers. Tom Musta (18): target-ppc: VSX Stage 4: Add VSX 2.07 Flag target-ppc: VSX Stage 4: Refactor lxsdx target-ppc: VSX Stage 4: Add lxsiwax, lxsiwzx and lxsspx target-ppc: VSX Stage 4: Refactor stxsdx target-ppc: VSX Stage 4: Add stxsiwx and stxsspx target-ppc: VSX Stage 4: Add xsaddsp and xssubsp target-ppc: VSX Stage 4: Add xsmulsp target-ppc: VSX Stage 4: Add xsdivsp target-ppc: VSX Stage 4: Add xsresp target-ppc: VSX Stage 4: Add xssqrtsp target-ppc: VSX Stage 4: add xsrsqrtesp target-ppc: VSX Stage 4: Add Scalar SP Fused Multiply-Adds target-ppc: VSX Stage 4: Add xscvsxdsp and xscvuxdsp target-ppc: VSX Stage 4: Add xxleqv, xxlnand and xxlorc target-ppc: Move To/From VSR Instructions target-ppc: Floating Merge Word Instructions target-ppc: Scalar Round to Single Precision target-ppc: Scalar Non-Signalling Conversions target-ppc/cpu.h | 4 +- target-ppc/fpu_helper.c | 222 ++++++++++++++++++++++++++++++------------- target-ppc/helper.h | 21 ++++ target-ppc/translate.c | 224 ++++++++++++++++++++++++++++++++++++++----- target-ppc/translate_init.c | 2 +- 5 files changed, 379 insertions(+), 94 deletions(-)
