Hi All, The clock controller module in the Zynq platform has the ability to halt and reset arbitrary devices, including the CPU. We use this feature to implement SMP Linux - the kernel halts CPU1 then rewrites the vector table to the secondary entry point and the resets+unhalts.
This series adds SMP support to the Zynq machine, and patches the Zynq SLCR (the clock controller) to have GPIOs connected to the CPUs. The GPIOs cause and ARM CPU reset. Only the reset side is implemented (which is good enough for SMP linux as it stands). Future work is to implement the halting behaviour as well. changed since v4 (PMM review): Convert to GPIO scheme Implemented custom secondary cpu reset OCM Macro cleanup changed since v3: Removed halting patches Reduced to minimal change needed for SMP Zynq Peter Crosthwaite (5): arm: zynq: Macroify OCM Base and Size arm: zynq: added SMP support zynq_slcr: Implement CPU reset arm: Implement reset GPIO. arm: zynq: Connect CPU resets to SLCR hw/arm/xilinx_zynq.c | 87 ++++++++++++++++++++++++++++++++++++++++------------ hw/misc/zynq_slcr.c | 16 ++++++++++ target-arm/cpu.c | 23 ++++++++++++++ target-arm/cpu.h | 8 +++-- 4 files changed, 112 insertions(+), 22 deletions(-) -- 1.8.5.3
