OK, here's the respin of the target-arm pullreq with the stupid
32-bit-CPUs-don't boot bug fixed, plus extra softfloat patches
which the PPC series on-list will need, and full FP A64 support.
I tested this version better, too :-)
Please pull; apologies again for the previous bug.
thanks
-- PMM
The following changes since commit f976b09ea249cccc3fd41c98aaf6512908db0bae:
PPC: Fix compilation with TCG debug (2013-12-22 19:15:55 +0100)
are available in the git repository at:
git://git.linaro.org/people/pmaydell/qemu-arm.git
tags/pull-target-arm-20140107
for you to fetch changes up to 096fc768184d5e9c47ccc4dd95d9f983fa83b9e1:
target-arm: A64: Add support for FCVT between half, single and double
(2014-01-07 19:18:08 +0000)
----------------------------------------------------------------
target-arm queue:
* further A64 decoder patches, including enabling the aarch64-linux-user
target; this includes full floating point support. Neon is not yet
supported.
* cadence UART model fixes.
* some minor bug fixes and cleanups.
* all the softfloat fixes required by the new A64 instructions;
several of these will also be used by PPC.
----------------------------------------------------------------
Alex Bennée (6):
target-arm: A64: add support for ld/st unsigned imm
target-arm: A64: add support for ld/st with reg offset
target-arm: A64: add support for ld/st with index
target-arm: A64: add support for add, addi, sub, subi
target-arm: A64: add support for move wide instructions
.travis.yml: Add aarch64-* targets
Alexander Graf (9):
target-arm: A64: add support for 3 src data proc insns
target-arm: A64: implement SVC, BRK
target-arm: aarch64: add support for ld lit
target-arm: A64: Add support for dumping AArch64 VFP register state
target-arm: A64: Add "Floating-point data-processing (2 source)" insns
target-arm: A64: Add "Floating-point data-processing (3 source)" insns
target-arm: A64: Add fmov (scalar, immediate) instruction
target-arm: Give the FPSCR rounding modes names
target-arm: A64: Add floating-point<->fixed-point instructions
Christoffer Dall (2):
arm_gic: Rename GIC_X_TRIGGER to GIC_X_EDGE_TRIGGER
hw: arm_gic: Introduce gic_set_priority function
Claudio Fontana (6):
target-arm: A64: add support for add/sub with carry
target-arm: A64: add support for conditional compare insns
linux-user: AArch64: define TARGET_CLONE_BACKWARDS
target-arm: A64: Add support for floating point compare
target-arm: A64: Add support for floating point conditional compare
target-arm: A64: Add support for floating point cond select
Michael Matz (1):
target-arm: A64: support for ld/st/cl exclusive
Michael S. Tsirkin (1):
target-arm: fix build with gcc 4.8.2
Peter Crosthwaite (13):
char/cadence_uart: Mark struct fields as public/private
char/cadence_uart: Add missing uart_update_state
char/cadence_uart: Fix reset.
char/cadence_uart: s/r_fifo/rx_fifo
char/cadence_uart: Simplify status generation
char/cadence_uart: Define Missing SR/ISR fields
char/cadence_uart: Remove TX timer & add TX FIFO state
char/cadence_uart: Fix can_receive logic
char/cadence_uart: Use the TX fifo for transmission
char/cadence_uart: Delete redundant rx rst logic
char/cadence_uart: Implement Tx flow control
target-arm: remove raw_read|write duplication
arm/xilinx_zynq: Always instantiate the GEMs
Peter Maydell (26):
target-arm: A64: add support for ld/st pair
target-arm: A64: Add decoder skeleton for FP instructions
target-arm: A64: implement FMOV
target-arm: Pull "add one cpreg to hashtable" into its own function
target-arm: Update generic cpreg code for AArch64
target-arm: Remove ARMCPU/CPUARMState from cpregs APIs used by decoder
target-arm: A64: Implement MRS/MSR/SYS/SYSL
target-arm: A64: Implement minimal set of EL0-visible sysregs
target-arm: Widen thread-local register state fields to 64 bits
target-arm: Widen exclusive-access support struct fields to 64 bits
default-configs: Add config for aarch64-linux-user
target-arm: A64: Fix vector register access on bigendian hosts
target-arm: Use VFP_BINOP macro for min, max, minnum, maxnum
softfloat: Fix exception flag handling for float32_to_float16()
softfloat: Add 16 bit integer to float conversions
softfloat: Make the int-to-float functions take exact-width types
softfloat: Only raise Invalid when conversions to int are out of range
softfloat: Fix factor 2 error for scalbn on denormal inputs
softfloat: Provide complete set of accessors for fp state
softfloat: Factor out RoundAndPackFloat16 and NormalizeFloat16Subnormal
softfloat: Add float16 <=> float64 conversion functions
softfloat: Refactor code handling various rounding modes
softfloat: Add support for ties-away rounding
target-arm: Ignore most exceptions from scalbn when doing fixpoint
conversion
target-arm: A64: Add 1-source 32-to-32 and 64-to-64 FP instructions
target-arm: A64: Add support for FCVT between half, single and double
Sergey Fedorov (1):
target-arm: use c13_context field for CONTEXTIDR
Tom Musta (5):
softfloat: Fix float64_to_uint64
softfloat: Add float32_to_uint64()
softfloat: Fix float64_to_uint64_round_to_zero
softfloat: Fix float64_to_uint32
softfloat: Fix float64_to_uint32_round_to_zero
Will Newton (6):
linux-user: AArch64: Use correct values for FPSR/FPCR in sigcontext
softfloat: Add float to 16bit integer conversions.
target-arm: Prepare VFP_CONV_FIX helpers for A64 uses
target-arm: Rename A32 VFP conversion helpers
target-arm: A64: Add extra VFP fixed point conversion helpers
target-arm: A64: Add floating-point<->integer conversion instructions
.travis.yml | 1 +
default-configs/aarch64-linux-user.mak | 3 +
fpu/softfloat.c | 1055 ++++++++---
hw/arm/xilinx_zynq.c | 17 +-
hw/char/cadence_uart.c | 153 +-
hw/intc/arm_gic.c | 27 +-
hw/intc/arm_gic_common.c | 4 +-
hw/intc/gic_internal.h | 7 +-
include/fpu/softfloat.h | 96 +-
include/hw/intc/arm_gic_common.h | 2 +-
linux-user/aarch64/syscall.h | 1 +
linux-user/aarch64/target_cpu.h | 5 +-
linux-user/arm/target_cpu.h | 2 +-
linux-user/main.c | 154 +-
linux-user/signal.c | 10 +-
target-arm/cpu.h | 122 +-
target-arm/cpu64.c | 6 +
target-arm/helper-a64.c | 45 +
target-arm/helper-a64.h | 4 +
target-arm/helper.c | 452 ++++-
target-arm/helper.h | 40 +-
target-arm/kvm-consts.h | 37 +
target-arm/machine.c | 12 +-
target-arm/neon_helper.c | 12 -
target-arm/translate-a64.c | 3106 +++++++++++++++++++++++++++++---
target-arm/translate.c | 112 +-
target-arm/translate.h | 2 +
27 files changed, 4662 insertions(+), 825 deletions(-)
create mode 100644 default-configs/aarch64-linux-user.mak
