On 12/20/2013 08:08 AM, Peter Maydell wrote:
>> In particular, opc = 2 && size = 2 should be unallocated.
>
> This is LDRSW (immediate), not unallocated, isn't it?
>
> I agree the decode logic isn't laid out the same as the ARM ARM,
> but I'm pretty sure it's correct.
Oops, typo: opc=3 && size=2. Basically,
if opc<1> == '0' then
// store or zero-extending load
memop = if opc<0> == '1' then MemOp_LOAD else MemOp_STORE;
regsize = if size == '11' then 64 else 32;
signed = FALSE;
else
if size == '11' then
memop = MemOp_PREFETCH;
if opc<0> == '1' then UnallocatedEncoding();
else
// sign-extending load
memop = MemOp_LOAD;
if size == '10' && opc<0> == '1' then UnallocatedEncoding();
this one ----^
r~
