Simplistic search and replace only. Cleanups to follow.
Signed-off-by: Richard Henderson <r...@twiddle.net>
---
target-s390x/translate.c | 154 +++++++++++++++++++++++------------------------
1 file changed, 77 insertions(+), 77 deletions(-)
diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index bc99a37..8fc8259 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -1754,20 +1754,20 @@ static ExitStatus op_clc(DisasContext *s, DisasOps *o)
switch (l + 1) {
case 1:
- tcg_gen_qemu_ld8u(cc_src, o->addr1, get_mem_index(s));
- tcg_gen_qemu_ld8u(cc_dst, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_UB);
+ tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_UB);
break;
case 2:
- tcg_gen_qemu_ld16u(cc_src, o->addr1, get_mem_index(s));
- tcg_gen_qemu_ld16u(cc_dst, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_BEUW);
+ tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_BEUW);
break;
case 4:
- tcg_gen_qemu_ld32u(cc_src, o->addr1, get_mem_index(s));
- tcg_gen_qemu_ld32u(cc_dst, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_BEUL);
+ tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_BEUL);
break;
case 8:
- tcg_gen_qemu_ld64(cc_src, o->addr1, get_mem_index(s));
- tcg_gen_qemu_ld64(cc_dst, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(cc_src, o->addr1, get_mem_index(s), MO_BEQ);
+ tcg_gen_qemu_ld_i64(cc_dst, o->in2, get_mem_index(s), MO_BEQ);
break;
default:
potential_page_fault(s);
@@ -1841,9 +1841,9 @@ static ExitStatus op_cs(DisasContext *s, DisasOps *o)
means that R1 is equal to the memory in all conditions. */
addr = get_address(s, 0, b2, d2);
if (is_64) {
- tcg_gen_qemu_ld64(o->out, addr, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, addr, get_mem_index(s), MO_BEQ);
} else {
- tcg_gen_qemu_ld32u(o->out, addr, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, addr, get_mem_index(s), MO_BEUL);
}
/* Are the memory and expected values (un)equal? Note that this setcond
@@ -1859,9 +1859,9 @@ static ExitStatus op_cs(DisasContext *s, DisasOps *o)
mem = tcg_temp_new_i64();
tcg_gen_movcond_i64(TCG_COND_EQ, mem, cc, z, o->in1, o->out);
if (is_64) {
- tcg_gen_qemu_st64(mem, addr, get_mem_index(s));
+ tcg_gen_qemu_st_i64(mem, addr, get_mem_index(s), MO_BEQ);
} else {
- tcg_gen_qemu_st32(mem, addr, get_mem_index(s));
+ tcg_gen_qemu_st_i64(mem, addr, get_mem_index(s), MO_BEUL);
}
tcg_temp_free_i64(z);
tcg_temp_free_i64(mem);
@@ -1891,8 +1891,8 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
outh = tcg_temp_new_i64();
outl = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(outh, addrh, get_mem_index(s));
- tcg_gen_qemu_ld64(outl, addrl, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(outh, addrh, get_mem_index(s), MO_BEQ);
+ tcg_gen_qemu_ld_i64(outl, addrl, get_mem_index(s), MO_BEQ);
/* Fold the double-word compare with arithmetic. */
cc = tcg_temp_new_i64();
@@ -1909,8 +1909,8 @@ static ExitStatus op_cdsg(DisasContext *s, DisasOps *o)
tcg_gen_movcond_i64(TCG_COND_EQ, meml, cc, z, regs[r3 + 1], outl);
tcg_temp_free_i64(z);
- tcg_gen_qemu_st64(memh, addrh, get_mem_index(s));
- tcg_gen_qemu_st64(meml, addrl, get_mem_index(s));
+ tcg_gen_qemu_st_i64(memh, addrh, get_mem_index(s), MO_BEQ);
+ tcg_gen_qemu_st_i64(meml, addrl, get_mem_index(s), MO_BEQ);
tcg_temp_free_i64(memh);
tcg_temp_free_i64(meml);
tcg_temp_free_i64(addrh);
@@ -1946,7 +1946,7 @@ static ExitStatus op_cvd(DisasContext *s, DisasOps *o)
tcg_gen_trunc_i64_i32(t2, o->in1);
gen_helper_cvd(t1, t2);
tcg_temp_free_i32(t2);
- tcg_gen_qemu_st64(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(t1, o->in2, get_mem_index(s), MO_BEQ);
tcg_temp_free_i64(t1);
return NO_EXIT;
}
@@ -2110,7 +2110,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
switch (m3) {
case 0xf:
/* Effectively a 32-bit load. */
- tcg_gen_qemu_ld32u(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUL);
len = 32;
goto one_insert;
@@ -2118,7 +2118,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
case 0x6:
case 0x3:
/* Effectively a 16-bit load. */
- tcg_gen_qemu_ld16u(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUW);
len = 16;
goto one_insert;
@@ -2127,7 +2127,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
case 0x2:
case 0x1:
/* Effectively an 8-bit load. */
- tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
len = 8;
goto one_insert;
@@ -2143,7 +2143,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
ccm = 0;
while (m3) {
if (m3 & 0x8) {
- tcg_gen_qemu_ld8u(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
tcg_gen_addi_i64(o->in2, o->in2, 1);
tcg_gen_deposit_i64(o->out, o->out, tmp, pos, 8);
ccm |= 0xff << pos;
@@ -2249,43 +2249,43 @@ static ExitStatus op_llgt(DisasContext *s, DisasOps *o)
static ExitStatus op_ld8s(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld8s(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_SB);
return NO_EXIT;
}
static ExitStatus op_ld8u(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld8u(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_UB);
return NO_EXIT;
}
static ExitStatus op_ld16s(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld16s(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BESW);
return NO_EXIT;
}
static ExitStatus op_ld16u(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld16u(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUW);
return NO_EXIT;
}
static ExitStatus op_ld32s(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld32s(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BESL);
return NO_EXIT;
}
static ExitStatus op_ld32u(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld32u(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEUL);
return NO_EXIT;
}
static ExitStatus op_ld64(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_ld64(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->out, o->in2, get_mem_index(s), MO_BEQ);
return NO_EXIT;
}
@@ -2360,9 +2360,9 @@ static ExitStatus op_lpsw(DisasContext *s, DisasOps *o)
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
- tcg_gen_qemu_ld32u(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEUL);
tcg_gen_addi_i64(o->in2, o->in2, 4);
- tcg_gen_qemu_ld32u(t2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_BEUL);
/* Convert the 32-bit PSW_MASK into the 64-bit PSW_MASK. */
tcg_gen_shli_i64(t1, t1, 32);
gen_helper_load_psw(cpu_env, t1, t2);
@@ -2379,9 +2379,9 @@ static ExitStatus op_lpswe(DisasContext *s, DisasOps *o)
t1 = tcg_temp_new_i64();
t2 = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(t1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t1, o->in2, get_mem_index(s), MO_BEQ);
tcg_gen_addi_i64(o->in2, o->in2, 8);
- tcg_gen_qemu_ld64(t2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t2, o->in2, get_mem_index(s), MO_BEQ);
gen_helper_load_psw(cpu_env, t1, t2);
tcg_temp_free_i64(t1);
tcg_temp_free_i64(t2);
@@ -2408,7 +2408,7 @@ static ExitStatus op_lm32(DisasContext *s, DisasOps *o)
TCGv_i64 t4 = tcg_const_i64(4);
while (1) {
- tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t, o->in2, get_mem_index(s), MO_BEUL);
store_reg32_i64(r1, t);
if (r1 == r3) {
break;
@@ -2430,7 +2430,7 @@ static ExitStatus op_lmh(DisasContext *s, DisasOps *o)
TCGv_i64 t4 = tcg_const_i64(4);
while (1) {
- tcg_gen_qemu_ld32u(t, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(t, o->in2, get_mem_index(s), MO_BEUL);
store_reg32h_i64(r1, t);
if (r1 == r3) {
break;
@@ -2451,7 +2451,7 @@ static ExitStatus op_lm64(DisasContext *s, DisasOps *o)
TCGv_i64 t8 = tcg_const_i64(8);
while (1) {
- tcg_gen_qemu_ld64(regs[r1], o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(regs[r1], o->in2, get_mem_index(s), MO_BEQ);
if (r1 == r3) {
break;
}
@@ -3015,9 +3015,9 @@ static ExitStatus op_soc(DisasContext *s, DisasOps *o)
r1 = get_field(s->fields, r1);
a = get_address(s, 0, get_field(s->fields, b2), get_field(s->fields, d2));
if (s->insn->data) {
- tcg_gen_qemu_st64(regs[r1], a, get_mem_index(s));
+ tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEQ);
} else {
- tcg_gen_qemu_st32(regs[r1], a, get_mem_index(s));
+ tcg_gen_qemu_st_i64(regs[r1], a, get_mem_index(s), MO_BEUL);
}
tcg_temp_free_i64(a);
@@ -3162,9 +3162,9 @@ static ExitStatus op_stcke(DisasContext *s, DisasOps *o)
tcg_gen_shli_i64(c2, c1, 56);
tcg_gen_shri_i64(c1, c1, 8);
tcg_gen_ori_i64(c2, c2, 0x10000);
- tcg_gen_qemu_st64(c1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(c1, o->in2, get_mem_index(s), MO_BEQ);
tcg_gen_addi_i64(o->in2, o->in2, 8);
- tcg_gen_qemu_st64(c2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(c2, o->in2, get_mem_index(s), MO_BEQ);
tcg_temp_free_i64(c1);
tcg_temp_free_i64(c2);
/* ??? We don't implement clock states. */
@@ -3232,7 +3232,7 @@ static ExitStatus op_stfl(DisasContext *s, DisasOps *o)
check_privileged(s);
f = tcg_const_i64(0xc0000000);
a = tcg_const_i64(200);
- tcg_gen_qemu_st32(f, a, get_mem_index(s));
+ tcg_gen_qemu_st_i64(f, a, get_mem_index(s), MO_BEUL);
tcg_temp_free_i64(f);
tcg_temp_free_i64(a);
return NO_EXIT;
@@ -3289,7 +3289,7 @@ static ExitStatus op_stnosm(DisasContext *s, DisasOps *o)
restart, we'll have the wrong SYSTEM MASK in place. */
t = tcg_temp_new_i64();
tcg_gen_shri_i64(t, psw_mask, 56);
- tcg_gen_qemu_st8(t, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(t, o->addr1, get_mem_index(s), MO_UB);
tcg_temp_free_i64(t);
if (s->fields->op == 0xac) {
@@ -3312,25 +3312,25 @@ static ExitStatus op_stura(DisasContext *s, DisasOps *o)
static ExitStatus op_st8(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st8(o->in1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_UB);
return NO_EXIT;
}
static ExitStatus op_st16(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st16(o->in1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_BEUW);
return NO_EXIT;
}
static ExitStatus op_st32(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st32(o->in1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_BEUL);
return NO_EXIT;
}
static ExitStatus op_st64(DisasContext *s, DisasOps *o)
{
- tcg_gen_qemu_st64(o->in1, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in1, o->in2, get_mem_index(s), MO_BEQ);
return NO_EXIT;
}
@@ -3356,7 +3356,7 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
case 0xf:
/* Effectively a 32-bit store. */
tcg_gen_shri_i64(tmp, o->in1, pos);
- tcg_gen_qemu_st32(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUL);
break;
case 0xc:
@@ -3364,7 +3364,7 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
case 0x3:
/* Effectively a 16-bit store. */
tcg_gen_shri_i64(tmp, o->in1, pos);
- tcg_gen_qemu_st16(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUW);
break;
case 0x8:
@@ -3373,7 +3373,7 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
case 0x1:
/* Effectively an 8-bit store. */
tcg_gen_shri_i64(tmp, o->in1, pos);
- tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
break;
default:
@@ -3382,7 +3382,7 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
while (m3) {
if (m3 & 0x8) {
tcg_gen_shri_i64(tmp, o->in1, pos);
- tcg_gen_qemu_st8(tmp, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
tcg_gen_addi_i64(o->in2, o->in2, 1);
}
m3 = (m3 << 1) & 0xf;
@@ -3403,9 +3403,9 @@ static ExitStatus op_stm(DisasContext *s, DisasOps *o)
while (1) {
if (size == 8) {
- tcg_gen_qemu_st64(regs[r1], o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), MO_BEQ);
} else {
- tcg_gen_qemu_st32(regs[r1], o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(regs[r1], o->in2, get_mem_index(s), MO_BEUL);
}
if (r1 == r3) {
break;
@@ -3428,7 +3428,7 @@ static ExitStatus op_stmh(DisasContext *s, DisasOps *o)
while (1) {
tcg_gen_shl_i64(t, regs[r1], t32);
- tcg_gen_qemu_st32(t, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(t, o->in2, get_mem_index(s), MO_BEUL);
if (r1 == r3) {
break;
}
@@ -3569,28 +3569,28 @@ static ExitStatus op_xc(DisasContext *s, DisasOps *o)
l++;
while (l >= 8) {
- tcg_gen_qemu_st64(o->in2, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_BEQ);
l -= 8;
if (l > 0) {
tcg_gen_addi_i64(o->addr1, o->addr1, 8);
}
}
if (l >= 4) {
- tcg_gen_qemu_st32(o->in2, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_BEUL);
l -= 4;
if (l > 0) {
tcg_gen_addi_i64(o->addr1, o->addr1, 4);
}
}
if (l >= 2) {
- tcg_gen_qemu_st16(o->in2, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_BEUW);
l -= 2;
if (l > 0) {
tcg_gen_addi_i64(o->addr1, o->addr1, 2);
}
}
if (l) {
- tcg_gen_qemu_st8(o->in2, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->in2, o->addr1, get_mem_index(s), MO_UB);
}
gen_op_movi_cc(s, 0);
return NO_EXIT;
@@ -3941,31 +3941,31 @@ static void wout_cond_e1e2(DisasContext *s, DisasFields
*f, DisasOps *o)
static void wout_m1_8(DisasContext *s, DisasFields *f, DisasOps *o)
{
- tcg_gen_qemu_st8(o->out, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_UB);
}
#define SPEC_wout_m1_8 0
static void wout_m1_16(DisasContext *s, DisasFields *f, DisasOps *o)
{
- tcg_gen_qemu_st16(o->out, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUW);
}
#define SPEC_wout_m1_16 0
static void wout_m1_32(DisasContext *s, DisasFields *f, DisasOps *o)
{
- tcg_gen_qemu_st32(o->out, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEUL);
}
#define SPEC_wout_m1_32 0
static void wout_m1_64(DisasContext *s, DisasFields *f, DisasOps *o)
{
- tcg_gen_qemu_st64(o->out, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->addr1, get_mem_index(s), MO_BEQ);
}
#define SPEC_wout_m1_64 0
static void wout_m2_32(DisasContext *s, DisasFields *f, DisasOps *o)
{
- tcg_gen_qemu_st32(o->out, o->in2, get_mem_index(s));
+ tcg_gen_qemu_st_i64(o->out, o->in2, get_mem_index(s), MO_BEUL);
}
#define SPEC_wout_m2_32 0
@@ -4121,7 +4121,7 @@ static void in1_m1_8u(DisasContext *s, DisasFields *f,
DisasOps *o)
{
in1_la1(s, f, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld8u(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_UB);
}
#define SPEC_in1_m1_8u 0
@@ -4129,7 +4129,7 @@ static void in1_m1_16s(DisasContext *s, DisasFields *f,
DisasOps *o)
{
in1_la1(s, f, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld16s(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESW);
}
#define SPEC_in1_m1_16s 0
@@ -4137,7 +4137,7 @@ static void in1_m1_16u(DisasContext *s, DisasFields *f,
DisasOps *o)
{
in1_la1(s, f, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld16u(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUW);
}
#define SPEC_in1_m1_16u 0
@@ -4145,7 +4145,7 @@ static void in1_m1_32s(DisasContext *s, DisasFields *f,
DisasOps *o)
{
in1_la1(s, f, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld32s(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BESL);
}
#define SPEC_in1_m1_32s 0
@@ -4153,7 +4153,7 @@ static void in1_m1_32u(DisasContext *s, DisasFields *f,
DisasOps *o)
{
in1_la1(s, f, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld32u(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEUL);
}
#define SPEC_in1_m1_32u 0
@@ -4161,7 +4161,7 @@ static void in1_m1_64(DisasContext *s, DisasFields *f,
DisasOps *o)
{
in1_la1(s, f, o);
o->in1 = tcg_temp_new_i64();
- tcg_gen_qemu_ld64(o->in1, o->addr1, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in1, o->addr1, get_mem_index(s), MO_BEQ);
}
#define SPEC_in1_m1_64 0
@@ -4323,70 +4323,70 @@ static void in2_sh64(DisasContext *s, DisasFields *f,
DisasOps *o)
static void in2_m2_8u(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_a2(s, f, o);
- tcg_gen_qemu_ld8u(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_UB);
}
#define SPEC_in2_m2_8u 0
static void in2_m2_16s(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_a2(s, f, o);
- tcg_gen_qemu_ld16s(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESW);
}
#define SPEC_in2_m2_16s 0
static void in2_m2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_a2(s, f, o);
- tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUW);
}
#define SPEC_in2_m2_16u 0
static void in2_m2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_a2(s, f, o);
- tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESL);
}
#define SPEC_in2_m2_32s 0
static void in2_m2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_a2(s, f, o);
- tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL);
}
#define SPEC_in2_m2_32u 0
static void in2_m2_64(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_a2(s, f, o);
- tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEQ);
}
#define SPEC_in2_m2_64 0
static void in2_mri2_16u(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_ri2(s, f, o);
- tcg_gen_qemu_ld16u(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUW);
}
#define SPEC_in2_mri2_16u 0
static void in2_mri2_32s(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_ri2(s, f, o);
- tcg_gen_qemu_ld32s(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BESL);
}
#define SPEC_in2_mri2_32s 0
static void in2_mri2_32u(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_ri2(s, f, o);
- tcg_gen_qemu_ld32u(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEUL);
}
#define SPEC_in2_mri2_32u 0
static void in2_mri2_64(DisasContext *s, DisasFields *f, DisasOps *o)
{
in2_ri2(s, f, o);
- tcg_gen_qemu_ld64(o->in2, o->in2, get_mem_index(s));
+ tcg_gen_qemu_ld_i64(o->in2, o->in2, get_mem_index(s), MO_BEQ);
}
#define SPEC_in2_mri2_64 0
--
1.8.3.1
