[Qemu-devel] [PATCH 4/5] target-s390: Simplify op_icm, op_stcm

[Richard Henderson]

Loads and stores can now be shared, along with the surrounding code.

Signed-off-by: Richard Henderson <r...@twiddle.net>
---
 target-s390x/translate.c | 27 ++++++++++++++++-----------
 1 file changed, 16 insertions(+), 11 deletions(-)

diff --git a/target-s390x/translate.c b/target-s390x/translate.c
index 3e88c23..aa7d351 100644
--- a/target-s390x/translate.c
+++ b/target-s390x/translate.c
@@ -2085,12 +2085,13 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
     int m3 = get_field(s->fields, m3);
     int pos, len, base = s->insn->data;
     TCGv_i64 tmp = tcg_temp_new_i64();
+    TCGMemOp mop;
     uint64_t ccm;
 
     switch (m3) {
     case 0xf:
         /* Effectively a 32-bit load.  */
-        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUL);
+        mop = MO_BEUL;
         len = 32;
         goto one_insert;
 
@@ -2098,7 +2099,7 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
     case 0x6:
     case 0x3:
         /* Effectively a 16-bit load.  */
-        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_BEUW);
+        mop = MO_BEUW;
         len = 16;
         goto one_insert;
 
@@ -2107,11 +2108,12 @@ static ExitStatus op_icm(DisasContext *s, DisasOps *o)
     case 0x2:
     case 0x1:
         /* Effectively an 8-bit load.  */
-        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), MO_UB);
+        mop = MO_UB;
         len = 8;
         goto one_insert;
 
     one_insert:
+        tcg_gen_qemu_ld_i64(tmp, o->in2, get_mem_index(s), mop);
         pos = base + ctz32(m3) * 8;
         tcg_gen_deposit_i64(o->out, o->out, tmp, pos, len);
         ccm = ((1ull << len) - 1) << pos;
@@ -3327,30 +3329,33 @@ static ExitStatus op_stcm(DisasContext *s, DisasOps *o)
     int m3 = get_field(s->fields, m3);
     int pos, base = s->insn->data;
     TCGv_i64 tmp = tcg_temp_new_i64();
+    TCGMemOp mop;
 
-    pos = base + ctz32(m3) * 8;
     switch (m3) {
     case 0xf:
         /* Effectively a 32-bit store.  */
-        tcg_gen_shri_i64(tmp, o->in1, pos);
-        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUL);
-        break;
+        mop = MO_BEUL;
+        goto one_store;
 
     case 0xc:
     case 0x6:
     case 0x3:
         /* Effectively a 16-bit store.  */
-        tcg_gen_shri_i64(tmp, o->in1, pos);
-        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_BEUW);
-        break;
+        mop = MO_BEUW;
+        goto one_store;
 
     case 0x8:
     case 0x4:
     case 0x2:
     case 0x1:
         /* Effectively an 8-bit store.  */
+        mop = MO_UB;
+        goto one_store;
+
+    one_store:
+        pos = base + ctz32(m3) * 8;
         tcg_gen_shri_i64(tmp, o->in1, pos);
-        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), MO_UB);
+        tcg_gen_qemu_st_i64(tmp, o->in2, get_mem_index(s), mop);
         break;
 
     default:
-- 
1.8.3.1